component
NCP81255MNTXG
Public Made by Adomby adom
onsemi DC-DC Converters, QFN-40(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+338−8@@ -1,13 +1,348 @@ {+ "schema_version": 1,+ "type": "component", "slug": "ncp81255mntxg",+ "title": "NCP81255MNTXG",+ "brief": "onsemi DC-DC Converters, QFN-40(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "onsemi DC-DC Converters, QFN-40(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "power management (pmic)", "ncp81255mntxg" ],+ "component": {+ "mpn": "NCP81255MNTXG",+ "manufacturer": "onsemi",+ "package": "QFN-40(5x5)",+ "pin_count": 44,+ "category": "Power Management (PMIC)",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589990317098098688",+ "parts": {+ "symbol": "ncp81255mntxg.kicad_sym",+ "footprint": "ncp81255mntxg.kicad_mod",+ "model_3d": "ncp81255mntxg.glb",+ "model_3d_step": "ncp81255mntxg.step",+ "lbr": "ncp81255mntxg.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "VR_HOT#",+ "type": "output",+ "description": "Thermal logic (open-drain) output asserted low on over-temperature detected on either TSENSE input. VOL \u2264 0.3 V; leakage \u00b11 \u00b5A when high-Z. Typical VRHOT assert threshold \u2248 472 mV at TSENSE."+ },+ {+ "number": "2",+ "name": "SDIO",+ "type": "bidirectional",+ "description": "Serial VID data interface (Intel IMVP8 SVID data line). Bidirectional open-drain data pin used by the CPU/PMIC controller."+ },+ {+ "number": "3",+ "name": "ALERT#",+ "type": "output",+ "description": "Serial VID ALERT# open-drain output. Asserted low by the regulator to alert the CPU controller (SVID master). Typical TSENSE Alert# assert threshold \u2248 491 mV."+ },+ {+ "number": "4",+ "name": "SCLK",+ "type": "input",+ "description": "Serial VID clock input (Intel IMVP8 SVID clock). Driven by the CPU/PMIC SVID master."+ },+ {+ "number": "5",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground. Connected to the source of the internal low-side FET; carries the switching return current."+ },+ {+ "number": "6",+ "name": "VR_RDY",+ "type": "output",+ "description": "Open-drain regulator-ready output. High indicates the controller is ready to accept Intel proprietary interface commands; requires external pull-up (e.g. 1 k\u03a9 to 3.3 V). VOL \u2264 0.3 V at 4 mA."+ },+ {+ "number": "7",+ "name": "VIN",+ "type": "power_in",+ "description": "Input voltage to the drain of the integrated high-side FET. Absolute max 30 V. Must be bypassed with \u226522 \u00b5F ceramic close to the pin."+ },+ {+ "number": "8",+ "name": "BST",+ "type": "power_in",+ "description": "Bootstrap capacitor node for the high-side gate driver. Cap required from this pin to SW; BST\u2212SW absolute max 6.5 V."+ },+ {+ "number": "9",+ "name": "GH",+ "type": "output",+ "description": "High-side FET gate driver output. Swings between SW and BST; internally driven, not for external MOSFET use."+ },+ {+ "number": "10",+ "name": "SW",+ "type": "power_out",+ "description": "Switch node - return path for the integrated high-side driver, internally connected to the source of the HS FET. Absolute max \u22120.3 V to 30 V (\u22122 V < 200 ns)."+ },+ {+ "number": "11",+ "name": "VIN",+ "type": "power_in",+ "description": "Input voltage to HS FET drain. Parallel with pins 7,12,13,14 and flag 42. Bypass with \u226522 \u00b5F ceramic close to the pin."+ },+ {+ "number": "12",+ "name": "VIN",+ "type": "power_in",+ "description": "Input voltage to HS FET drain. Parallel with pins 7,11,13,14 and flag 42."+ },+ {+ "number": "13",+ "name": "VIN",+ "type": "power_in",+ "description": "Input voltage to HS FET drain. Parallel with pins 7,11,12,14 and flag 42."+ },+ {+ "number": "14",+ "name": "VIN",+ "type": "power_in",+ "description": "Input voltage to HS FET drain. Parallel with pins 7,11,12,13 and flag 42."+ },+ {+ "number": "15",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground - source of internal LS FET. Parallel with pins 5,16,17,18,19,20,26 and flag 43."+ },+ {+ "number": "16",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground - source of internal LS FET."+ },+ {+ "number": "17",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground - source of internal LS FET."+ },+ {+ "number": "18",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground - source of internal LS FET."+ },+ {+ "number": "19",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground - source of internal LS FET."+ },+ {+ "number": "20",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground - source of internal LS FET."+ },+ {+ "number": "21",+ "name": "SW",+ "type": "power_out",+ "description": "Switch node output - interconnection between internal HS and LS FETs. Connect to external inductor. Parallel with pins 10,22,23."+ },+ {+ "number": "22",+ "name": "SW",+ "type": "power_out",+ "description": "Switch node output - interconnection between internal HS and LS FETs. Connect to external inductor."+ },+ {+ "number": "23",+ "name": "SW",+ "type": "power_out",+ "description": "Switch node output - interconnection between internal HS and LS FETs. Connect to external inductor."+ },+ {+ "number": "24",+ "name": "GL",+ "type": "output",+ "description": "Low-side FET gate driver output. Internally driven; parallel with pin 25 and flag 44."+ },+ {+ "number": "25",+ "name": "GL",+ "type": "output",+ "description": "Low-side FET gate driver output. Internally driven; parallel with pin 24 and flag 44."+ },+ {+ "number": "26",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground - source of internal LS FET."+ },+ {+ "number": "27",+ "name": "PVCC",+ "type": "power_in",+ "description": "Gate-driver supply. Bypass with \u22654.7 \u00b5F ceramic to GND as close as possible to the pin. Analog supply absolute max 6.5 V."+ },+ {+ "number": "28",+ "name": "IMAX",+ "type": "input",+ "description": "ICCMAX register programming input. A resistor to ground scales/encodes the ICCMAX value read by the SVID master."+ },+ {+ "number": "29",+ "name": "TSENSE",+ "type": "input",+ "description": "External temperature sense network input. Sourced with ~120 \u00b5A bias; NTC network to GND sets the sensed temperature used for VR_HOT#/ALERT#."+ },+ {+ "number": "30",+ "name": "DOSC/ADDR/VBOOT",+ "type": "input",+ "description": "Multi-function programming pin: sets switching frequency FSW, the Intel proprietary interface address, and the VBOOT value during start-up. A resistor to GND programs all three values per the datasheet look-up table."+ },+ {+ "number": "31",+ "name": "PSYS",+ "type": "input",+ "description": "System power signal input. A resistor to ground scales the applied battery-charger/system-power signal. ADC range 0-2 V."+ },+ {+ "number": "32",+ "name": "VSP",+ "type": "input",+ "description": "Differential output-voltage sense positive input to the internal \u2212gm amplifier. Kelvin to VCC_SENSE. Input range \u22120.3 V to 3.0 V."+ },+ {+ "number": "33",+ "name": "VSN",+ "type": "input",+ "description": "Differential output-voltage sense negative input. Kelvin to VSS_SENSE. Input range \u22120.3 V to 0.3 V."+ },+ {+ "number": "34",+ "name": "COMP",+ "type": "passive",+ "description": "Loop compensation node - RC network to GND sets the error-amp/control-loop response."+ },+ {+ "number": "35",+ "name": "ILIM",+ "type": "input",+ "description": "Current-limit programming input. Resistor sets the OCP threshold; ILIMIT threshold internally 1.275-1.325 V."+ },+ {+ "number": "36",+ "name": "CSN",+ "type": "input",+ "description": "Differential current sense negative input (across output inductor DCR/CS resistor). Also serves as the CSP/CSN ZCD comparator negative input."+ },+ {+ "number": "37",+ "name": "CSP",+ "type": "input",+ "description": "Differential current sense positive input. Kelvin to the SW side of the sense element. Also serves as the ZCD comparator positive input."+ },+ {+ "number": "38",+ "name": "IOUT",+ "type": "output",+ "description": "IOUT (current-monitor) analog output / gain programming pin. Resistor to GND sets the IOUT gm gain (nominal 1.0 mS)."+ },+ {+ "number": "39",+ "name": "VCC",+ "type": "power_in",+ "description": "Analog/control-circuit supply input. 4.75 V-5.25 V nominal. Bypass with \u22651 \u00b5F ceramic close to the controller. Quiescent 10 mA typ (EN = H)."+ },+ {+ "number": "40",+ "name": "EN",+ "type": "input",+ "description": "Enable input. Upper (enable) threshold \u22650.8 V typ, lower threshold \u22640.3 V, 300 mV hysteresis. Also feeds the VFF (input voltage feed-forward) path."+ },+ {+ "number": "41",+ "name": "GND",+ "type": "power_in",+ "description": "Exposed thermal/analog ground flag (Flag). Ground of internal control circuits - must be soldered to the analog ground plane."+ },+ {+ "number": "42",+ "name": "VIN",+ "type": "power_in",+ "description": "Exposed VIN flag (Flag) - internally connected to HS FET drain, parallel with pins 7,11-14. Bypass with \u226522 \u00b5F ceramic close to the pin."+ },+ {+ "number": "43",+ "name": "PGND",+ "type": "power_in",+ "description": "Exposed PGND flag (Flag) - source of internal LS FET, parallel with pins 5,15-20,26."+ },+ {+ "number": "44",+ "name": "GL",+ "type": "output",+ "description": "Exposed GL flag (Flag) - gate driver output for internal LS FET, parallel with pins 24,25."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589990317098098688",+ "pages": 20,+ "sha256": "2fc79e9f921d081b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 44,+ "described": 44,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "onsemi",+ "Package": "QFN-40(5x5)",+ "Category": "Power Management (PMIC)",+ "Pins": "44"+ }+ },+ "variants": [+ {+ "mpn": "NCP81255MNTXG",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "ncp81255mntxg"+ ],+ "discovery_pitch": "NCP81255MNTXG (onsemi) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +360,5 @@ "docs/ncp81255mntxg-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }