component
NCP81255MNTXG
Public Made by Adomby adom
onsemi DC-DC Converters, QFN-40(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+18−15@@ -32,7 +32,7 @@ "number": "1", "name": "VR_HOT#", "type": "output",- "description": "Thermal logic (open-drain) output asserted low on over-temperature detected on either TSENSE input. VOL \u2264 0.3 V; leakage \u00b11 \u00b5A when high-Z. Typical VRHOT assert threshold \u2248 472 mV at TSENSE."+ "description": "Thermal logic (open-drain) output asserted low on over-temperature detected on either TSENSE input. VOL ≤ 0.3 V; leakage ±1 µA when high-Z. Typical VRHOT assert threshold ≈ 472 mV at TSENSE." }, { "number": "2",@@ -44,7 +44,7 @@ "number": "3", "name": "ALERT#", "type": "output",- "description": "Serial VID ALERT# open-drain output. Asserted low by the regulator to alert the CPU controller (SVID master). Typical TSENSE Alert# assert threshold \u2248 491 mV."+ "description": "Serial VID ALERT# open-drain output. Asserted low by the regulator to alert the CPU controller (SVID master). Typical TSENSE Alert# assert threshold ≈ 491 mV." }, { "number": "4",@@ -62,19 +62,19 @@ "number": "6", "name": "VR_RDY", "type": "output",- "description": "Open-drain regulator-ready output. High indicates the controller is ready to accept Intel proprietary interface commands; requires external pull-up (e.g. 1 k\u03a9 to 3.3 V). VOL \u2264 0.3 V at 4 mA."+ "description": "Open-drain regulator-ready output. High indicates the controller is ready to accept Intel proprietary interface commands; requires external pull-up (e.g. 1 kΩ to 3.3 V). VOL ≤ 0.3 V at 4 mA." }, { "number": "7", "name": "VIN", "type": "power_in",- "description": "Input voltage to the drain of the integrated high-side FET. Absolute max 30 V. Must be bypassed with \u226522 \u00b5F ceramic close to the pin."+ "description": "Input voltage to the drain of the integrated high-side FET. Absolute max 30 V. Must be bypassed with ≥22 µF ceramic close to the pin." }, { "number": "8", "name": "BST", "type": "power_in",- "description": "Bootstrap capacitor node for the high-side gate driver. Cap required from this pin to SW; BST\u2212SW absolute max 6.5 V."+ "description": "Bootstrap capacitor node for the high-side gate driver. Cap required from this pin to SW; BST−SW absolute max 6.5 V." }, { "number": "9",@@ -86,13 +86,13 @@ "number": "10", "name": "SW", "type": "power_out",- "description": "Switch node - return path for the integrated high-side driver, internally connected to the source of the HS FET. Absolute max \u22120.3 V to 30 V (\u22122 V < 200 ns)."+ "description": "Switch node - return path for the integrated high-side driver, internally connected to the source of the HS FET. Absolute max −0.3 V to 30 V (−2 V < 200 ns)." }, { "number": "11", "name": "VIN", "type": "power_in",- "description": "Input voltage to HS FET drain. Parallel with pins 7,12,13,14 and flag 42. Bypass with \u226522 \u00b5F ceramic close to the pin."+ "description": "Input voltage to HS FET drain. Parallel with pins 7,12,13,14 and flag 42. Bypass with ≥22 µF ceramic close to the pin." }, { "number": "12",@@ -188,7 +188,7 @@ "number": "27", "name": "PVCC", "type": "power_in",- "description": "Gate-driver supply. Bypass with \u22654.7 \u00b5F ceramic to GND as close as possible to the pin. Analog supply absolute max 6.5 V."+ "description": "Gate-driver supply. Bypass with ≥4.7 µF ceramic to GND as close as possible to the pin. Analog supply absolute max 6.5 V." }, { "number": "28",@@ -200,7 +200,7 @@ "number": "29", "name": "TSENSE", "type": "input",- "description": "External temperature sense network input. Sourced with ~120 \u00b5A bias; NTC network to GND sets the sensed temperature used for VR_HOT#/ALERT#."+ "description": "External temperature sense network input. Sourced with ~120 µA bias; NTC network to GND sets the sensed temperature used for VR_HOT#/ALERT#." }, { "number": "30",@@ -218,13 +218,13 @@ "number": "32", "name": "VSP", "type": "input",- "description": "Differential output-voltage sense positive input to the internal \u2212gm amplifier. Kelvin to VCC_SENSE. Input range \u22120.3 V to 3.0 V."+ "description": "Differential output-voltage sense positive input to the internal −gm amplifier. Kelvin to VCC_SENSE. Input range −0.3 V to 3.0 V." }, { "number": "33", "name": "VSN", "type": "input",- "description": "Differential output-voltage sense negative input. Kelvin to VSS_SENSE. Input range \u22120.3 V to 0.3 V."+ "description": "Differential output-voltage sense negative input. Kelvin to VSS_SENSE. Input range −0.3 V to 0.3 V." }, { "number": "34",@@ -260,13 +260,13 @@ "number": "39", "name": "VCC", "type": "power_in",- "description": "Analog/control-circuit supply input. 4.75 V-5.25 V nominal. Bypass with \u22651 \u00b5F ceramic close to the controller. Quiescent 10 mA typ (EN = H)."+ "description": "Analog/control-circuit supply input. 4.75 V-5.25 V nominal. Bypass with ≥1 µF ceramic close to the controller. Quiescent 10 mA typ (EN = H)." }, { "number": "40", "name": "EN", "type": "input",- "description": "Enable input. Upper (enable) threshold \u22650.8 V typ, lower threshold \u22640.3 V, 300 mV hysteresis. Also feeds the VFF (input voltage feed-forward) path."+ "description": "Enable input. Upper (enable) threshold ≥0.8 V typ, lower threshold ≤0.3 V, 300 mV hysteresis. Also feeds the VFF (input voltage feed-forward) path." }, { "number": "41",@@ -278,7 +278,7 @@ "number": "42", "name": "VIN", "type": "power_in",- "description": "Exposed VIN flag (Flag) - internally connected to HS FET drain, parallel with pins 7,11-14. Bypass with \u226522 \u00b5F ceramic close to the pin."+ "description": "Exposed VIN flag (Flag) - internally connected to HS FET drain, parallel with pins 7,11-14. Bypass with ≥22 µF ceramic close to the pin." }, { "number": "43",@@ -360,5 +360,8 @@ "docs/ncp81255mntxg-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }