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NCP81161MNTBG

Public Made by Adom

by adom

onsemi Gate Drivers, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCP81161MNTBG

onsemi · Gate Drivers · DFN-8-EP(2x2)

NCP81161MNTBG from onsemi, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST power_out Floating bootstrap supply for the high-side gate driver, with the bootstrap capacitor connected between BST and SW; BST is rated 35 V wrt GND (40 V for up to 50 ns) and 15 V wrt SW.
2 PWM input Three-state PWM control input (Low = low-side FET enabled, Mid = diode emulation enabled, High = high-side FET enabled), with Low ≤ 0.7 V, Mid 1.3 V to 2.7 V, High ≥ 3.4 V, and an absolute maximum of 6.5 V.
3 EN bidirectional Logic enable input (high enables the part, low disables it) with VIH ≥ 2.0 V and VIL ≤ 1.0 V and a 6.5 V absolute maximum, which also carries a fault signal back to the controller on OVP/UVLO/POR faults.
4 VCC power_in Main supply input with 4.5 V to 13.2 V operating range and a 15 V absolute maximum; connect a bypass capacitor (printed as 0.1 F in the source text) from this pin to ground.
5 DRVL output Low-side gate drive output for the low-side MOSFET gate, rated from -0.3 V DC (-5 V for under 200 ns) up to VCC + 0.3 V.
6 GND power_in Bias and reference ground to which all signals are referenced; the datasheet labels this pin as the QFN flag and requires the driver GND to be placed close to the low-side MOSFET source.
7 SW passive Switch node connected to the high-side MOSFET source and low-side MOSFET drain and serving as the bootstrap supply return; rated 35 V DC (40 V for up to 50 ns), -5 V DC (-10 V for 200 ns).
8 DRVH output High-side gate drive output for the high-side MOSFET gate, rated from -0.3 V wrt SW (-2 V for under 200 ns) up to BST + 0.3 V.
9 FLAG unconnected Thermal flag (exposed pad) with no electrical connection to the IC, to be connected to the ground plane for heat dissipation.

Key specifications

Parameter Value
Manufacturer onsemi
Package DFN-8-EP(2x2)
Category Motor Driver ICs
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Operation Voltage VCC 4.5 13.2 V 4
Power ON Reset Threshold 2.75 3.2 V 4
VCC Start Threshold 3.8 4.35 4.5 V 4
VCC UVLO Hysteresis 150 200 250 mV 4
Output Overvoltage Trip Threshold at Startup 2.1 2.25 2.4 V 4
Normal Mode Icc + Ibst Icc + Ibst 10 mA EN = 5 V, PWM = OSC, Fsw = 100 KHz, Cload = 3 nF for DRVH, 3 nF for DRVL 4
Standby Current (EN = GND) Icc + Ibst 0.5 1.4 mA EN = GND 4
Standby Current (EN HIGH, PWM LOW) ICC + IBST 2 mA EN = HIGH, PWM = LOW, No loading on DRVH & DRVL 4
Standby Current (EN HIGH, PWM HIGH) ICC + IBST 2 mA EN = HIGH, PWM = HIGH, No loading on DRVH & DRVL 4
Bootstrap Diode Forward Voltage 0.1 0.4 0.6 V VCC = 12 V, forward bias current = 2 mA 4
PWM Input High 3.4 V 4
PWM Mid-State 1.3 2.7 V 4
PWM Input Low 0.7 V 4
DRVH Output Impedance, Sourcing Current (VCC = 12 V) 1.9 3 VBST − VSW = 12 V 4
DRVH Output Impedance, Sinking Current (VCC = 12 V) 1 1.7 VBST − VSW = 12 V 4
DRVH Rise Time (VCC = 12 V) trDRVH 16 30 ns VVCC = 12 V, 3 nF load, VBST−VSW = 12 V 4
DRVH Fall Time (VCC = 12 V) tfDRVH 11 25 ns VVCC = 12 V, 3 nF load, VBST−VSW = 12 V 4
DRVH Turn-Off Propagation Delay (12 V section) tpdlDRVH 8 30 ns CLOAD = 3 nF 4
DRVH Turn-On Propagation Delay (12 V section) tpdhDRVH 30 ns CLOAD = 3 nF 4
SW Pull Down Resistance (12 V section) 45 k SW to PGND 4
DRVH Pull Down Resistance (12 V section) 45 k DRVH to SW, BST−SW = 0 V 4
LOW SIDE DRIVER Output Impedance, Sourcing Current (VCC = 12 V) 2 3 VCC = 12 V (section) 5
LOW SIDE DRIVER Output Impedance, Sinking Current (VCC = 12 V) 0.7 1.5 VCC = 12 V (section) 5
DRVL Rise Time (VCC = 12 V) trDRVL 16 35 ns CLOAD = 3 nF 5
DRVL Fall Time (VCC = 12 V) tfDRVL 11 20 ns CLOAD = 3 nF 5
DRVL Turn-Off Propagation Delay (12 V section) tpdlDRVL 35 ns CLOAD = 3 nF 5
DRVL Turn-On Propagation Delay (12 V section) tpdhDRVL 8 30 ns CLOAD = 3 nF 5
DRVL Pull Down Resistance (12 V section) 45 k DRVL to PGND, VCC = PGND 5
EN Input Voltage High 2 V 5
EN Input Voltage Low 1 V 5
EN Hysteresis 500 mV 5
Normal Mode Bias Current -1 1 A 5
Enable Pin Sink Current 4 30 mA 5
Enable Pin Propagation Delay Time 20 40 ns 5
SW Node Leakage Current 20 A 5
Zero Cross Detection Threshold Voltage -6 mV SW to −20 mV, ramp slowly until BG goes off (Start in DCM mode) (Note 3) 5
VCC Main Supply Voltage Input VCC -0.3 15 V 3
BST Bootstrap Supply Voltage BST 35 V wrt GND 3
BST Bootstrap Supply Voltage (≤50 ns) BST 40 V 40 V ≤ 50 ns, wrt GND 3
BST Bootstrap Supply Voltage vs SW BST−SW -0.3 15 V wrt SW 3
SW Switching Node SW -5 35 V 3
SW Switching Node (transient high) SW 40 V 40 V ≤ 50 ns 3
SW Switching Node (transient low) SW -10 V −10 V (200 ns) 3
DRVH High Side Driver Output DRVH -0.3 V Max BST+0.3 V; min wrt SW 3
DRVH High Side Driver Output (transient) DRVH -2 V <200 ns wrt SW 3
DRVL Low Side Driver Output DRVL -0.3 V Max VCC+0.3 V; DC 3
DRVL Low Side Driver Output (transient) DRVL -5 V <200 ns 3
PWM DRVH and DRVL Control Input PWM -0.3 6.5 V 3
EN Enable Pin EN -0.3 6.5 V 3
GND Ground GND 0 0 V 3
Operating Junction Temperature Range TJ 0 150 °C Note 2 3
Operating Ambient Temperature Range TA -10 125 °C 3
Maximum Storage Temperature Range TSTG -55 150 °C 3
BST−SWN Operating Range BST−SWN 4.5 13.2 V 4
BST Operating Range BST 4.5 30 V 4
SWN Operating Range SWN 0 21 V 4
Thermal Characteristic RJA RJA 74 °C/W Note 1: I in2 Cu, 1 oz thickness 3
DRVH Turn-On Propagation Delay (12 V section, tpdhDRVH) tpdhDRVH 30 ns CLOAD = 3 nF 4
ZCD Blanking Timer 250 ns 4

CAD (KiCad official)

  • Symbol: NCP81161MNTBG
  • Footprint: Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm
  • 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: ncp81161mntbg-etched.step / ncp81161mntbg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp81161mntbg.step / ncp81161mntbg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (9 pp, sha256 f4c60cab1756ec0d, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF