component
NCP5183DR2G
Public Made by Adomby adom
onsemi Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCP5183DR2G
onsemi · Gate Drivers · SOIC-8
NCP5183DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HIN | input | High side logic input, with logic-high threshold of 2.5 V min and logic-low threshold of 1.2 V max, and input voltage limited to GND to VCC − 2 V. |
| 2 | LIN | input | Low side logic input, with logic-high threshold of 2.5 V min and logic-low threshold of 1.2 V max, and input voltage limited to GND to VCC − 2 V. |
| 3 | GND | power_in | Ground reference; all device voltages are referenced to this pin. |
| 4 | DRVL | output | Low side gate drive output for the external low-side MOSFET, swinging between GND and VCC with 4.3 A peak source/sink capability. |
| 5 | VCC | power_in | Main power supply for the device, with recommended range of 10 V to 17 V, absolute maximum of 18 V, and VCC UVLO thresholds of 7.8 V to 9.8 V (rising). |
| 6 | HB | power_in | Bootstrap return and high side floating supply return, with recommended bridge pin voltage of −1 V to 580 V and extended allowable negative swing to −10 V. |
| 7 | DRVH | output | High side gate drive output for the external high-side MOSFET, referenced to HB, with 4.3 A peak source/sink capability. |
| 8 | VB | power_in | Bootstrap power supply for the high side driver, with recommended VB − VHB of 10 V to 17 V, absolute maximum VB−VHB of 18 V, and VB pin absolute maximum of 618 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC UVLO threshold, VCC rising | VCCon | 7.8 | 8.8 | 9.8 | V | VCC rising | 4 |
| VCC UVLO threshold, VCC falling | VCCoff | 7.2 | 8.3 | 9.1 | V | VCC falling | 4 |
| VB UVLO threshold, VB rising | VBon | 7.8 | 8.8 | 9.8 | V | VB rising | 4 |
| VB UVLO threshold, VB falling | VBoff | 7.2 | 8.3 | 9.1 | V | VB falling | 4 |
| VCC pin operating current | ICC1 | 520 | 700 | µA | f = 20 kHz, CL = 1 nF | 4 | |
| VB pin operating current | IB1 | 700 | 800 | µA | f = 20 kHz, CL = 1 nF | 4 | |
| VCC pin quiescent current | ICC2 | 95 | 160 | µA | VLIN = VHIN = 0 V | 4 | |
| VB pin quiescent current | IB2 | 65 | 100 | µA | VLIN = VHIN = 0 V | 4 | |
| Logic High Input Current | IxIN+ | 25 | 50 | µA | VxIN = 5 V | 4 | |
| Input Pull Down Resistance | RxIN | 100 | 250 | kΩ | VxIN = 5 V | 4 | |
| Turn On Propagation Delay | tON | 120 | 200 | ns | 4 | ||
| Turn Off Propagation Delay | tOFF | 120 | 200 | ns | 4 | ||
| Delay Matching | tMT | 0 | 50 | ns | Pulse width = 1 µs | 4 | |
| Output Voltage Rise Time | tr | 12 | 40 | ns | 10% to 90%, CL = 1 nF | 5 | |
| Output Voltage Fall Time | tf | 12 | 40 | ns | 90% to 10%, CL = 1 nF | 5 | |
| Negative HB pin Voltage | VHBneg | -8 | -7 | V | PW ≤ tON, VCC = VB = 10 V | 5 | |
| Supply voltage absolute maximum (VCC input voltage range) | VCC | -0.3 | 18 | V | 3 | ||
| Input voltage on LIN and HIN pins | VLIN, VHIN | -0.3 | 18 | V | 3 | ||
| High Side Boot pin Voltage | VB | 618 | V | 3 | |||
| High Side Floating Voltage | VB, VHB | -0.3 | 18 | V | 3 | ||
| Allowable output slew rate | dVHB/dt | 50 | V/ns | 3 | |||
| Maximum Operating Junction Temperature | TJ(max) | 150 | °C | 3 | |||
| Storage Temperature Range | TSTG | -55 | 150 | °C | 3 | ||
| ESD Capability, Human Body Model | ESDHBM | 3 | kV | Note 1: AEC-Q100-002 (EIA/JESD22-A114) | 3 | ||
| ESD Capability, Charged Device Model | ESDCDM | 1 | kV | Note 1: AEC-Q100-11 (EIA/JESD22-C101E) | 3 | ||
| Lead Temperature Soldering Reflow (Pb-Free) | TSLD | 260 | °C | Note 2 | 3 | ||
| Input Voltage Range | VCC | 10 | 17 | V | 3 | ||
| High Side Floating Voltage | VB, VHB | 10 | 17 | V | 3 | ||
| High Side Bridge pin Voltage | VHB | -1 | 580 | V | 3 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 3 | ||
| Thermal Resistance, Junction-to-Air (SO8) | RJA | 183 | °C/W | SO8, Note 4: copper area 645 mm2 (1 in2), 1 oz Cu, FR4 PCB | 3 |
CAD (KiCad official)
- Symbol:
NCP5183DR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp5183dr2g-etched.step/ncp5183dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp5183dr2g.step/ncp5183dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (16 pp, sha256
4f5aac1fbb4e37d7, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).