NCP51530ADR2G

{
  "slug": "ncp51530adr2g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management ics",
    "ncp51530adr2g",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ncp51530adr2g.kicad_sym",
    "ncp51530adr2g.kicad_mod",
    "ncp51530adr2g.glb",
    "ncp51530adr2g.step",
    "ncp51530adr2g.lbr",
    "docs/hero.png",
    "docs/ncp51530adr2g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ncp51530adr2g-hero.glb",
    "ncp51530adr2g-hero.overlay.json",
    "ncp51530adr2g-etched.glb"
  ],
  "component": {
    "mpn": "NCP51530ADR2G",
    "manufacturer": "onsemi",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Power Management ICs",
    "subcategory": "Gate Drive ICs",
    "datasheet": "https://www.onsemi.com/pdf/datasheet/ncp51530a-d.pdf",
    "parts": {
      "symbol": "ncp51530adr2g.kicad_sym",
      "footprint": "ncp51530adr2g.kicad_mod",
      "model_3d": "ncp51530adr2g-hero.glb",
      "model_3d_plain": "ncp51530adr2g-etched.glb",
      "model_3d_step": "ncp51530adr2g-etched.step",
      "model_3d_step_plain": "ncp51530adr2g.step",
      "lbr": "ncp51530adr2g.lbr"
    },
    "distributor_links": {
      "lcsc": "C603750",
      "digikey": "NCP51530ADR2GOSTR-ND",
      "mouser": "863-NCP51530ADR2G"
    },
    "distributor_check": {
      "checked_at": "2026-10-28T21:36:04Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "NCP51530ADR2GOSTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "863-NCP51530ADR2G",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "HIN",
        "type": "input",
        "description": "High side input; TTL/CMOS compatible with 3.3 V or 5 V logic, input range GND to VCC−2 V recommended and −5 V to VCC+0.3 V absolute maximum, with an internal pull-down (175 kΩ typical)."
      },
      {
        "number": "2",
        "name": "LIN",
        "type": "input",
        "description": "Low side input; TTL/CMOS compatible with 3.3 V or 5 V logic, input range GND to VCC−2 V recommended and −5 V to VCC+0.3 V absolute maximum, with an internal pull-down (175 kΩ typical)."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for all voltages on the device; all absolute maximum and recommended voltages are referenced to this pin."
      },
      {
        "number": "4",
        "name": "LO",
        "type": "output",
        "description": "Low side gate drive output, sourcing up to 3.5 A and sinking up to 3 A peak, with an output voltage range of −0.3 V to VCC+0.3 V."
      },
      {
        "number": "5",
        "name": "VCC",
        "type": "power_in",
        "description": "Low side and logic supply; recommended operating range is 10 V to 17 V, with a 20 V absolute maximum, and UVLO turn-on at 9.1 V typical."
      },
      {
        "number": "6",
        "name": "HB",
        "type": "power_in",
        "description": "High side supply return (floating bridge pin); recommended voltage range is −1 V to 700 V, and the allowable slew rate is 50 V/ns."
      },
      {
        "number": "7",
        "name": "HO",
        "type": "output",
        "description": "High side gate drive output, sourcing up to 3.5 A and sinking up to 3 A peak, with an output voltage between VHB−0.3 V and VB+0.3 V."
      },
      {
        "number": "8",
        "name": "VB",
        "type": "power_in",
        "description": "High side bootstrap supply; recommended VB−VHB range is 10 V to 17 V, with a 720 V absolute maximum boot pin voltage and UVLO turn-on at 8.5 V typical."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers and names were taken from Table 1 (PIN DESCRIPTION SOIC 8 PACKAGE) on page 2, which is t; The HB pin is described in the datasheet as the 'High side supply return'. The type 'power_in' is my"
        ],
        "pages_sent": 26,
        "cost_usd": 0.0946,
        "at": "2026-10-28T21:35:50"
      },
      "datasheet": {
        "url": "https://www.onsemi.com/pdf/datasheet/ncp51530a-d.pdf",
        "pages": 26,
        "sha256": "b711720d6925ff4f",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ncp51530adr2g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-28",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ncp51530adr2g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "340bcf16aa3a90d45dc6e446e4b6b588b5413493cce1fce67769f22b4f3540cd",
        "checked": "2026-10-28",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "SOIC-8 NB (CASE 751-07)",
      "source_page": 24,
      "D": {
        "nom_mm": 4.9,
        "range_mm": [
          4.8,
          5.0
        ]
      },
      "E1": {
        "nom_mm": 3.9,
        "range_mm": [
          3.8,
          4.0
        ]
      },
      "E": {
        "nom_mm": 6.0,
        "range_mm": [
          5.8,
          6.2
        ]
      },
      "e": {
        "nom_mm": 1.27,
        "range_mm": [
          null,
          null
        ]
      },
      "A": {
        "nom_mm": 1.55,
        "range_mm": [
          1.35,
          1.75
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "ncp51530adr2g.step",
        "verdict": "PASS",
        "reasons": [
          "height and body within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}