component
NCP51530ADR2G
Public Made by Adomby adom
onsemi Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NCP51530ADR2G
onsemi · Gate Drive ICs · SOIC-8
NCP51530ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HIN | input | High side input; TTL/CMOS compatible with 3.3 V or 5 V logic, input range GND to VCC−2 V recommended and −5 V to VCC+0.3 V absolute maximum, with an internal pull-down (175 kΩ typical). |
| 2 | LIN | input | Low side input; TTL/CMOS compatible with 3.3 V or 5 V logic, input range GND to VCC−2 V recommended and −5 V to VCC+0.3 V absolute maximum, with an internal pull-down (175 kΩ typical). |
| 3 | GND | power_in | Ground reference for all voltages on the device; all absolute maximum and recommended voltages are referenced to this pin. |
| 4 | LO | output | Low side gate drive output, sourcing up to 3.5 A and sinking up to 3 A peak, with an output voltage range of −0.3 V to VCC+0.3 V. |
| 5 | VCC | power_in | Low side and logic supply; recommended operating range is 10 V to 17 V, with a 20 V absolute maximum, and UVLO turn-on at 9.1 V typical. |
| 6 | HB | power_in | High side supply return (floating bridge pin); recommended voltage range is −1 V to 700 V, and the allowable slew rate is 50 V/ns. |
| 7 | HO | output | High side gate drive output, sourcing up to 3.5 A and sinking up to 3 A peak, with an output voltage between VHB−0.3 V and VB+0.3 V. |
| 8 | VB | power_in | High side bootstrap supply; recommended VB−VHB range is 10 V to 17 V, with a 720 V absolute maximum boot pin voltage and UVLO turn-on at 8.5 V typical. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range (recommended) | VCC | 10 | 17 | V | 6 | ||
| High side floating voltage (recommended) | VB-VHB | 10 | 17 | V | 6 | ||
| High side bridge pin voltage (recommended) | VHB | -1 | 700 | V | 6 | ||
| Operating junction temperature range (recommended) | TJ | -40 | 125 | °C | 6 | ||
| Input voltage range (absolute max) | VCC | -0.3 | 20 | V | All voltages referenced to GND | 5 | |
| High side boot pin voltage (absolute max) | VB | -0.3 | 720 | V | All voltages referenced to GND | 5 | |
| High side floating voltage (absolute max) | VB-VHB | -0.3 | 20 | V | All voltages referenced to GND | 5 | |
| Low side drive output voltage (absolute max) | VLO | -0.3 | V | Upper limit printed as VCC + 0.3 V | 5 | ||
| Drive input voltage (absolute max) | VLIN, VHIN | -5 | V | Upper limit printed as VCC + 0.3 V | 5 | ||
| Allowable HB slew rate | dVHB/dt | 50 | V/ns | 5 | |||
| Junction temperature (absolute max) | TJ(MAX) | 150 | °C | 5 | |||
| Storage temperature range | TSTG | -55 | 150 | °C | 5 | ||
| Lead temperature soldering | 260 | °C | Reflow (SMD styles only), Pb-Free versions | 5 | |||
| VCC quiescent current | ICCQ | 0.15 | 0.25 | mA | VLIN=VHIN=0 | 6 | |
| VCC operating current | ICCO | 0.7 | 1 | mA | f = 500 kHz, CLOAD = 0 | 6 | |
| Boot voltage quiescent current | IBQ | 0.1 | 0.15 | mA | VLIN = VHIN = 0 V | 6 | |
| Boot voltage operating current | IBO | 0.7 | 1 | mA | f = 500 kHz, CLOAD = 0 | 6 | |
| HB to GND quiescent current | IHBQ | 6 | 11 | A | VHS = VHB = 700 V | 6 | |
| Input rising threshold | VHIT | 2.3 | 2.7 | 3.1 | V | 6 | |
| Input falling threshold | VLIT | 1 | 1.4 | 1.8 | V | 6 | |
| Input pulldown resistance | RIN | 100 | 175 | 250 | k | VXIN = 5 V | 6 |
| VCC UVLO ON threshold (rising) | VCCon | 8.6 | 9.1 | 9.6 | V | VCC rising | 6 |
| VB UVLO ON threshold (rising) | VBon | 8 | 8.5 | 9 | V | VB rising | 6 |
| High side startup time | Tstartup | 10 | s | Time between VB > UVLO and 1st HO pulse | 6 | ||
| Low level output voltage (LO) | VLOL | 0.125 | V | ILO = 100 mA | 6 | ||
| High level output voltage (LO) | VLOH | 0.15 | V | ILO = −100 mA, VLOH = VCC − VLO | 6 | ||
| Peak source current (LO) | ILOpullup | 3.5 | A | VLO = 0 V | 6 | ||
| Peak sink current (LO) | ILOpulldown | 3 | A | VLO = 12 V | 7 | ||
| Low level output voltage (HO) | VHOL | 0.125 | V | IHO = 100 mA | 7 | ||
| High level output voltage (HO) | VHOH | 0.15 | V | IHO = −100 mA, VHOH = VHB − VHO | 7 | ||
| Peak source current (HO) | IHOpullup | 3.5 | A | VHO = 0 V | 7 | ||
| Peak sink current (HO) | IHOpulldown | 3 | A | VHO = 12 V | 7 | ||
| Rise time LO, HO | TR | 8 | 15 | ns | Cload = 1000 pF | 7 | |
| Fall time LO, HO | TF | 8 | 15 | ns | Cload = 1000 pF | 7 | |
| Delay matching, LI ON, HI OFF | TMON | 7 | ns | Pulse width = 1 s | 7 | ||
| Delay matching, LI OFF, HI ON | TMOFF | 7 | ns | Pulse width = 1 s | 7 | ||
| Minimum input filter (NCP51530A) | TFT | 30 | 40 | ns | VXIN = 5 V; input pulse width above which output change occurs | 7 | |
| VLI falling to VLO falling (NCP51530A) | TDLFF | 60 | 100 | ns | Cload = 0; minimum on/off-time to register as valid change = 50 ns | 7 | |
| VHI falling to VHO falling (NCP51530A) | TDHFF | 60 | 100 | ns | Cload = 0; minimum on/off-time to register as valid change = 50 ns | 7 | |
| VLI rising to VLO rising (NCP51530A) | TDLRR | 60 | 100 | ns | Cload = 0; minimum on/off-time to register as valid change = 50 ns | 7 | |
| VHI rising to VHO rising (NCP51530A) | TDHRR | 60 | 100 | ns | Cload = 0; minimum on/off-time to register as valid change = 50 ns | 7 | |
| Input voltage hysteresis | VIHYS | 1.3 | V | 6 | |||
| VCC hysteresis | VCChys | 0.5 | V | 6 | |||
| VB hysteresis | VBhyst | 0.5 | V | 6 | |||
| Thermal resistance, junction to air, SOIC8 | RJA | 183 | °C/W | SOIC8 package (Note 3) | 6 |
CAD (KiCad official)
- Symbol:
NCP51530ADR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp51530adr2g-etched.step/ncp51530adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp51530adr2g.step/ncp51530adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (26 pp, sha256
b711720d6925ff4f, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NCP51530ADR2G
**onsemi** · Gate Drive ICs · SOIC-8
NCP51530ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HIN | input | High side input; TTL/CMOS compatible with 3.3 V or 5 V logic, input range GND to VCC−2 V recommended and −5 V to VCC+0.3 V absolute maximum, with an internal pull-down (175 kΩ typical). |
| 2 | LIN | input | Low side input; TTL/CMOS compatible with 3.3 V or 5 V logic, input range GND to VCC−2 V recommended and −5 V to VCC+0.3 V absolute maximum, with an internal pull-down (175 kΩ typical). |
| 3 | GND | power_in | Ground reference for all voltages on the device; all absolute maximum and recommended voltages are referenced to this pin. |
| 4 | LO | output | Low side gate drive output, sourcing up to 3.5 A and sinking up to 3 A peak, with an output voltage range of −0.3 V to VCC+0.3 V. |
| 5 | VCC | power_in | Low side and logic supply; recommended operating range is 10 V to 17 V, with a 20 V absolute maximum, and UVLO turn-on at 9.1 V typical. |
| 6 | HB | power_in | High side supply return (floating bridge pin); recommended voltage range is −1 V to 700 V, and the allowable slew rate is 50 V/ns. |
| 7 | HO | output | High side gate drive output, sourcing up to 3.5 A and sinking up to 3 A peak, with an output voltage between VHB−0.3 V and VB+0.3 V. |
| 8 | VB | power_in | High side bootstrap supply; recommended VB−VHB range is 10 V to 17 V, with a 720 V absolute maximum boot pin voltage and UVLO turn-on at 8.5 V typical. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range (recommended) | VCC | 10 | | 17 | V | | 6 |
| High side floating voltage (recommended) | VB-VHB | 10 | | 17 | V | | 6 |
| High side bridge pin voltage (recommended) | VHB | -1 | | 700 | V | | 6 |
| Operating junction temperature range (recommended) | TJ | -40 | | 125 | °C | | 6 |
| Input voltage range (absolute max) | VCC | -0.3 | | 20 | V | All voltages referenced to GND | 5 |
| High side boot pin voltage (absolute max) | VB | -0.3 | | 720 | V | All voltages referenced to GND | 5 |
| High side floating voltage (absolute max) | VB-VHB | -0.3 | | 20 | V | All voltages referenced to GND | 5 |
| Low side drive output voltage (absolute max) | VLO | -0.3 | | | V | Upper limit printed as VCC + 0.3 V | 5 |
| Drive input voltage (absolute max) | VLIN, VHIN | -5 | | | V | Upper limit printed as VCC + 0.3 V | 5 |
| Allowable HB slew rate | dVHB/dt | | | 50 | V/ns | | 5 |
| Junction temperature (absolute max) | TJ(MAX) | | | 150 | °C | | 5 |
| Storage temperature range | TSTG | -55 | | 150 | °C | | 5 |
| Lead temperature soldering | | | | 260 | °C | Reflow (SMD styles only), Pb-Free versions | 5 |
| VCC quiescent current | ICCQ | | 0.15 | 0.25 | mA | VLIN=VHIN=0 | 6 |
| VCC operating current | ICCO | | 0.7 | 1 | mA | f = 500 kHz, CLOAD = 0 | 6 |
| Boot voltage quiescent current | IBQ | | 0.1 | 0.15 | mA | VLIN = VHIN = 0 V | 6 |
| Boot voltage operating current | IBO | | 0.7 | 1 | mA | f = 500 kHz, CLOAD = 0 | 6 |
| HB to GND quiescent current | IHBQ | | 6 | 11 | A | VHS = VHB = 700 V | 6 |
| Input rising threshold | VHIT | 2.3 | 2.7 | 3.1 | V | | 6 |
| Input falling threshold | VLIT | 1 | 1.4 | 1.8 | V | | 6 |
| Input pulldown resistance | RIN | 100 | 175 | 250 | k | VXIN = 5 V | 6 |
| VCC UVLO ON threshold (rising) | VCCon | 8.6 | 9.1 | 9.6 | V | VCC rising | 6 |
| VB UVLO ON threshold (rising) | VBon | 8 | 8.5 | 9 | V | VB rising | 6 |
| High side startup time | Tstartup | | 10 | | s | Time between VB > UVLO and 1st HO pulse | 6 |
| Low level output voltage (LO) | VLOL | | 0.125 | | V | ILO = 100 mA | 6 |
| High level output voltage (LO) | VLOH | | 0.15 | | V | ILO = −100 mA, VLOH = VCC − VLO | 6 |
| Peak source current (LO) | ILOpullup | | 3.5 | | A | VLO = 0 V | 6 |
| Peak sink current (LO) | ILOpulldown | | 3 | | A | VLO = 12 V | 7 |
| Low level output voltage (HO) | VHOL | | 0.125 | | V | IHO = 100 mA | 7 |
| High level output voltage (HO) | VHOH | | 0.15 | | V | IHO = −100 mA, VHOH = VHB − VHO | 7 |
| Peak source current (HO) | IHOpullup | | 3.5 | | A | VHO = 0 V | 7 |
| Peak sink current (HO) | IHOpulldown | | 3 | | A | VHO = 12 V | 7 |
| Rise time LO, HO | TR | | 8 | 15 | ns | Cload = 1000 pF | 7 |
| Fall time LO, HO | TF | | 8 | 15 | ns | Cload = 1000 pF | 7 |
| Delay matching, LI ON, HI OFF | TMON | | | 7 | ns | Pulse width = 1 s | 7 |
| Delay matching, LI OFF, HI ON | TMOFF | | | 7 | ns | Pulse width = 1 s | 7 |
| Minimum input filter (NCP51530A) | TFT | 30 | 40 | | ns | VXIN = 5 V; input pulse width above which output change occurs | 7 |
| VLI falling to VLO falling (NCP51530A) | TDLFF | | 60 | 100 | ns | Cload = 0; minimum on/off-time to register as valid change = 50 ns | 7 |
| VHI falling to VHO falling (NCP51530A) | TDHFF | | 60 | 100 | ns | Cload = 0; minimum on/off-time to register as valid change = 50 ns | 7 |
| VLI rising to VLO rising (NCP51530A) | TDLRR | | 60 | 100 | ns | Cload = 0; minimum on/off-time to register as valid change = 50 ns | 7 |
| VHI rising to VHO rising (NCP51530A) | TDHRR | | 60 | 100 | ns | Cload = 0; minimum on/off-time to register as valid change = 50 ns | 7 |
| Input voltage hysteresis | VIHYS | | 1.3 | | V | | 6 |
| VCC hysteresis | VCChys | | 0.5 | | V | | 6 |
| VB hysteresis | VBhyst | | 0.5 | | V | | 6 |
| Thermal resistance, junction to air, SOIC8 | RJA | | 183 | | °C/W | SOIC8 package (Note 3) | 6 |
## CAD (KiCad official)
- Symbol: `NCP51530ADR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ncp51530adr2g-etched.step` / `ncp51530adr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp51530adr2g.step` / `ncp51530adr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncp51530a-d.pdf) (26 pp, sha256 `b711720d6925ff4f`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ncp51530adr2g-datasheet.pdf)