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NCP51510MNTAG

Public Made by Adom

by adom

onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCP51510MNTAG

onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-10-EP(3x3)

NCP51510MNTAG from onsemi, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VRO output Buffered output of the VRI reference input, capable of sourcing and sinking ±5 mA and active when VRI > 0.45 V and VCC is above UVLO.
2 VCC power_in Regulator analog power input, specified at 2.7 V to 3.6 V, to be bypassed to AGND with a 1 µF or greater ceramic capacitor.
3 AGND power_in Analog ground.
4 VRI input External reference input for the VTT output, with an input voltage range of 0.5 V to 1.5 V.
5 PGOOD output Open-drain VTT power-good output that requires an external pull-up resistor to a stable supply rail.
6 VTTS input Remote sense input for VTT that provides accurate feedback sensing of the VTT output, connected to the positive terminal of the output capacitors.
7 SS input CMOS-compatible suspend shutdown input where logic HIGH enables the regulator and logic LOW shuts it down; connect to VDDQ for normal operation.
8 PGND power_in Power ground, internally connected to the low-side MOSFET.
9 VTT output Regulated power output with a continuous RMS current rating of ±1.6 A (100 s) and ±2.5 A for 1 s per the absolute maximum ratings.
10 PVCC power_in Regulator power input, specified at 1.1 V to 3.6 V, internally connected to the high-side MOSFET.
11 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer onsemi
Package DFN-10-EP(3x3)
Category Power Management (PMIC)
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
PVCC to PGND -0.3 4.3 V 2
VCC to AGND VCC -0.3 4.3 V 2
VRI, VRO, SS, PGOOD to AGND (max printed as VCC + 0.3) -0.3 V 2
VTT to PGND (max printed as PVCC + 0.3) -0.3 V 2
VTTS to AGND (max printed as PVCC + 0.3) VTTS -0.3 V 2
PGND to AGND PGND -0.3 0.3 V 2
Storage Temperature Tstg -65 150 °C 2
Operating Junction Temperature Range TJ -40 125 °C 2
ESD Capability, Human Body Model ESDHBM 2000 V 2
ESD Capability, Machine Model ESDMM 200 V 2
VTT Output Continuous RMS Current -1.6 1.6 A 100 sec 2
VTT Output Continuous RMS Current -2.5 2.5 A 1 sec 2
VTT Output Voltage Range VTT, VTTS 0.5 1.5 V 3
PVCC Input Voltage Range (Power) PVCC 1.1 3.6 V 3
VCC Input Voltage Range (Analog) VCC 2.7 3.6 V 3
Logic Voltage Range SS, PGOOD (max printed as VCC) 0 V 3
Operating Ambient Temperature Range TA -40 125 °C 3
VTT Output Voltage Range VTT 0.5 1.5 V PVCC > (VTT + VDROPOUT) 3
VTT Load Regulation VLOAD -4 4 mV −1 A ≤ ITT ≤ +1 A 3
Feedback-Voltage Error VTTS -17 17 VRI to VTTS, ITT = ±200 mA; TA = −40°C to 125°C 3
Current-Limit Threshold ITT LIMIT 1.8 3 4.2 A TA = −40°C to +125°C 3
VCC UVLO Threshold VCC UVLO 2.5 2.7 2.9 V Wake-up, rising edge 3
PVCC UVLO Threshold PVCC UVLO 0.9 1.1 V Wake-up, rising edge 3
VRI Input Voltage Range VRI 0.5 1.5 V 3
VRI Input-Bias Current IRI -1 1 µA TA = +25°C 3
VRO Output Voltage (printed as VRI −10 / VRI +10, relative to VRI) VRO -10 10 mV VCC = 3.3 V, IRO = 0 3
VRO Load Regulation VRO -20 20 IRO = ±5 mA 3
SS Logic Input Current ISS -1 1 µA SS = VCC or 0 V, TA = +25°C 3
VTT Output MOSFET RDS(on) High-side (source) RDS(on) 140 250 mΩ ITT = +100 mA 3
VTT Output MOSFET RDS(on) Low-side (sink) RDS(on) 140 250 mΩ ITT = −100 mA 3
Quiescent PVCC Current IPVCC 0.4 10 mA No Load 3
Quiescent VCC Current ICC 0.7 1.3 VRI > 0.45 V, No Load 3
Shutdown PVCC Current IPVCC SD 0.1 10 µA SS = 0 V 3
Shutdown VCC Current ICC SD 50 100 SS = 0V, VRI = 0 V 3
Shutdown VCC Current ICC SD 350 600 SS = 0V, VRI > 0.45 V 3
PGOOD Lower Trip Threshold -200 -150 -100 mV With respect to feedback threshold, hysteresis = 12 mV 4
PGOOD Upper Trip Threshold 100 150 200 mV 4
PGOOD Start-up Delay 1 2 3.5 ms Start-up rising edge, VTTS within ±100 mV of the feedback threshold 4
VRI UVLO Voltage VRI UVLO 350 450 VRI, rising edge 4
PGOOD Propagation Delay TPGOOD 5 10 35 µs VTTS forced 25 mV beyond PGOOD trip threshold 4
Power Dissipation (10-pin DFN) 1951 mW TA = 70C 2

CAD (KiCad official)

  • Symbol: NCP51510MNTAG
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: ncp51510mntag-etched.step / ncp51510mntag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp51510mntag.step / ncp51510mntag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 ecf0ea6cff380418, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF