component
NCP51200MNTXG
Public Made by Adomby adom
onsemi Linear Voltage Regulators (LDO), DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+106docs/hero.pngdocs/ncp51200mntxg-datasheet.pdf+4050ncp51200mntxg-etched.glbncp51200mntxg-hero.glbncp51200mntxg-hero.overlay.json+317ncp51200mntxg.glbncp51200mntxg.kicad_mod+259ncp51200mntxg.kicad_sym+57ncp51200mntxg.lbr+134ncp51200mntxg.step+2991package.json+211page.json+217viewers/footprint.html+1viewers/symbol.html+1README.mdadded+106@@ -0,0 +1,106 @@+# NCP51200MNTXG++**onsemi** · Linear Voltage Regulators (LDO) · DFN-10(3x3)++NCP51200MNTXG from onsemi, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VRI | input | VTT external reference input, set to VDDQ/2 through a resistor network, with a 0.5 to 1.8 V range. |+| 2 | PVCC | power_in | Power input internally connected to the output source MOSFET, with a 1.1 to 3.5 V range. |+| 3 | VTT | power_out | Power output of the linear regulator. |+| 4 | PGND | power_in | Power ground internally connected to the output sink MOSFET. |+| 5 | VTTS | input | VTT sense input providing accurate remote feedback sensing of VTT, connected to the remote DDR termination bypass capacitors. |+| 6 | VRO | output | Independent buffered VTT reference output that sources and sinks over 5 mA, connected to GND through a 0.1 uF ceramic capacitor. |+| 7 | EN | input | CMOS-compatible shutdown control input, with logic high = enable and logic low = shutdown, connected to VDDQ for normal operation. |+| 8 | GND | power_in | Common ground. |+| 9 | PGOOD | output | Open-drain power good output that goes high when VTT is within ±20% of VRO, needing a pull-up resistor (100 kΩ in the text). |+| 10 | VCC | power_in | Analog power supply input (2.375 to 5.5 V recommended), connected to GND through a 1 to 4.7 uF ceramic capacitor. |+| 11 | THERMAL PAD | passive | Exposed pad for thermal connection, to be connected to the ground plane using multiple vias for maximum power dissipation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | DFN-10(3x3) |+| Category | Power Management ICs |+| Pins | 11 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| VCC Supply Current | IVCC | | 0.7 | 1 | mA | TA = +25°C, EN = 3.3 V, No Load | 3 |+| VCC Shutdown Current | IVCC SHD | | 65 | 80 | µA | TA = +25°C, EN = 0 V, VRI = 0 V, No Load | 3 |+| VCC Shutdown Current | IVCC SHD | | 200 | 400 | µA | TA = +25°C, EN = 0 V, VRI > 0.4 V, No Load | 3 |+| VCC UVLO Threshold | VUVLO | 2.15 | 2.3 | 2.375 | V | Wake-up, TA = +25°C | 3 |+| PVCC Supply Current | IPVCC | | 1 | 50 | µA | TA = +25°C, EN = 3.3 V, No Load | 3 |+| PVCC Shutdown Current | IPVCC SHD | | 0.1 | 50 | µA | TA = +25°C, EN = 0 V, No Load | 3 |+| VTT Output Offset Voltage | VOS | -15 | | 15 | mV | VRO = 1.25 V (DDR1), ITT = 0 A | 3 |+| VTT Voltage Tolerance to VRO | | -25 | | 25 | mV | -2 A ≤ ITT ≤ +2 A | 3 |+| Source Current Limit | | 3 | | 4.5 | A | VTTS = 90% * VRO | 3 |+| Sink Current Limit | | 3.5 | | 5.5 | A | VTTS = 110% * VRO | 3 |+| Discharge MOSFET On-resistance | RDIS | | 18 | 25 | Ω | VRI = 0 V, VTT = 0.3 V, EN = 0 V, TA = +25°C | 3 |+| VRI Voltage Range | VRI | 0.5 | | 1.8 | V | | 3 |+| VRI UVLO Voltage | VRI UVLO | 360 | 390 | 435 | mV | VRI rising | 3 |+| VRO Voltage Tolerance to VRI | | -15 | | 15 | mV | IRO = ±10 mA, 0.6 V ≤ VRI ≤ 1.25 V | 3 |+| VRO Source Current Limit | | 10 | | 40 | mA | VRO = 0 V | 3 |+| VRO Sink Current Limit | | 10 | | 40 | mA | VRO = 0 V | 3 |+| PGOOD Lower Threshold (wrt VRO) | | -23.5 | -20 | -17.5 | % | | 4 |+| PGOOD Upper Threshold (wrt VRO) | | 17.5 | 20 | 23.5 | % | | 4 |+| PGOOD Output Low Voltage | | | | 0.4 | V | IGOOD = 4 mA | 4 |+| PGOOD Leakage Current | | | | 1 | µA | VTTS = VRI (PGOOD = True), PGOOD = VCC + 0.2 V | 4 |+| EN Logic Input Threshold High | VIH | 1.7 | | | V | EN Logic high | 5 |+| EN Logic Input Threshold Low | VIL | | | 0.3 | V | EN Logic low | 5 |+| EN Logic Leakage Current | IILEAK | -1 | | 1 | µA | EN pin, TA = +25°C | 5 |+| VRI Input-bias Current | IRI | | | 1 | µA | EN = 3.3 V | 3 |+| Soft-start Current Limit Timeout | TSS | | 200 | | µs | | 3 |+| VRI UVLO Hysteresis | VRI HYS | | 60 | | mV | | 3 |+| VCC UVLO Hysteresis | | | 50 | | mV | Hysteresis | 3 |+| PGOOD Hysteresis | | | 5 | | % | | 4 |+| PGOOD Start-up Delay | | | 2 | | ms | Start-up rising edge, VTTS within 15% of VRO | 4 |+| PGOOD = False Delay | | | 10 | | µs | VTTS is beyond ±20% PGOOD trip thresholds | 4 |+| EN Hysteresis Voltage | VENHYS | | 0.5 | | V | EN pin | 5 |+| Thermal Shutdown Temperature | TSD | | 150 | | °C | | 5 |+| Thermal Shutdown Hysteresis | TSH | | 25 | | °C | | 5 |+| Supply Voltage | VCC | 2.375 | | 5.5 | V | | 3 |+| VRO Voltage Range | VRO | -0.1 | | 1.8 | V | | 3 |+| VRI Voltage Range | VRI | 0.5 | | 1.8 | V | | 3 |+| PVCC, VTT, VTTS, EN, PGOOD Voltage Range | | -0.1 | | 3.5 | V | | 3 |+| PGND Voltage Range | PGND | -0.1 | | 0.1 | V | | 3 |+| Operating Free-Air Temperature | TA | -40 | | 125 | °C | | 3 |+| VCC, PVCC, VTT, VTTS, VRI, VRO Voltage | | -0.3 | | 6 | V | | 2 |+| EN, PGOOD Voltage | | -0.3 | | 6 | V | | 2 |+| PGND to GND | | -0.3 | | 0.3 | V | | 2 |+| Storage Temperature | TSTG | -55 | | 150 | °C | | 2 |+| Operating Junction Temperature | TJ | | | 150 | °C | | 2 |+| ESD Capability, Human Body Model | ESDHBM | | | 2000 | V | | 2 |+| Power Rating | | | | 1.92 | W | TA = 25°C, 10-Pin DFN | 2 |+| Power Rating | | | | 0.79 | W | TA = +85°C, 10-Pin DFN | 2 |+| Junction-to-ambient thermal resistance | RθJA | | 53.9 | | °C/W | DFN 3x3mm 10 pins, 1S2P JEDEC JESD51-7 PCB | 2 |+| Junction-to-case (top) thermal resistance | RθJC(top) | | 95.5 | | °C/W | | 2 |+| Junction-to-board thermal resistance | RθJB | | 32.3 | | °C/W | 1mm from package | 2 |+| Junction-to-top thermal resistance | ψJT | | 4.3 | | °C/W | | 2 |+| Junction-to-case (bot) thermal resistance | RθJC(bot) | | 14.2 | | °C/W | | 2 |++## CAD (KiCad official)++- Symbol: `NCP51200MNTXG`+- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`+- 3D model: DFN-10(3x3) (KiCad packages3D, STEP)+- 3D model files: `ncp51200mntxg-etched.step` / `ncp51200mntxg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp51200mntxg.step` / `ncp51200mntxg.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncp51200mntx-d.pdf) (11 pp, sha256 `f1f00267673b0f73`, retrieved 2026-10-22, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ncp51200mntxg-datasheet.pdf)
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The NCP/NCV51200 maintains a fast transient response and only requires a minimum output capacitance of 20 μF. The NCP/NCV51200 supports a remote sensing function and all power requirements for DDR VTT bus termination. The NCP/NCV51200 can also be used in low-power chipsets and graphics processor cores that require dynamically adjustable output voltages.
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