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NCP5104DR2G

Public Made by Adom

by adom

onsemi Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsncp5104dr2gfactory-2.0.0extractor-text
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Contents

README

markdown

NCP5104DR2G

onsemi · Gate Drive ICs · SOIC-8

NCP5104DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low-side and main power supply, with a gate drive supply range of 10 V to 20 V (absolute maximum -0.3 to 20 V).
2 IN input Logic input compatible with 3.3 V and 5 V logic, with up to VCC swing allowed (-1.0 V to VCC + 0.3 V) and a typical 200 kOhm internal pull-down.
3 SD input Logic input for shutdown, allowed from -1.0 V to VCC + 0.3 V.
4 GND power_in Ground.
5 DRV_LO output Low-side gate drive output with 250 mA source / 500 mA sink capability, swinging -0.3 V to VCC + 0.3 V.
6 BRIDGE passive Bootstrap return or high-side floating supply return, rated -1 V to 600 V, with negative swing allowed to -10 V for signal propagation.
7 DRV_HI output High-side gate drive output with 250 mA source / 500 mA sink capability, swinging from VBRIDGE - 0.3 V to VBOOT + 0.3 V.
8 VBOOT power_in Bootstrap power supply for the high-side driver, rated -1 V to 620 V, with VBOOT-VBRIDGE floating supply of -0.3 V to 20 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Main power supply voltage VCC -0.3 20 V 3
Allowable negative bridge pin voltage for IN_LO signal propagation to DRV_LO VBRIDGE -10 V see characterization curves for detailed results 3
High voltage BOOT pin VBOOT -1 620 V 3
High voltage BRIDGE pin VBRIDGE -1 600 V 3
Floating supply voltage VBOOT−VBRIDGE -0.3 20 V 3
Allowable output slew rate dVBRIDGE/dt 50 V/ns 3
Main transient power supply voltage VCC_transient 23 V IVCC_max = 5 mA during 10 ms 3
ESD capability HBM model (all pins except pins 6−7−8) ESD 2 kV HBM model (all pins except pins 6−7−8 in 8) 3
ESD capability machine model (all pins except pins 6−7−8) ESD 200 V Machine model (all pins except pins 6−7−8) 3
Thermal resistance junction-to-air SO-8 RJA 178 C/W SO-8 3
Storage temperature range TST -55 150 C 3
Maximum operating junction temperature TJ_max 150 C 3
Output resistor source ROH 30 60 Typical value @ 25C 4
Output resistor sink ROL 10 20 Typical value @ 25C 4
High level output voltage VDRV_H 0.7 1.6 V VBIAS−VDRV_XX @ IDRV_XX = 20 mA 4
Low level output voltage VDRV_L 0.2 0.6 V VDRV_XX @ IDRV_XX = 20 mA 4
Turn-on propagation delay tON 620 800 ns Vbridge = 0 V (Note 3) 4
Turn-off propagation delay tOFF 100 170 ns Vbridge = 0 V or 50 V (Note 4) 4
Shutdown propagation delay, when Shutdown is enabled tsd_en 100 170 ns when Shutdown is enabled 4
Shutdown propagation delay, when Shutdown is disabled tsd_dis 620 800 ns when Shutdown is disabled 4
Output voltage rise time (from 10% to 90%) tr 85 160 ns @ VCC = 15 V with 1 nF load 4
Output voltage fall time (from 90% to 10%) tf 35 75 ns @ VCC = 15 V with 1 nF load 4
Propagation delay matching between the High side and the Low side t 10 45 ns @ 25C (Note 5) 4
Internal fixed dead time DT 400 520 650 ns (Note 6) 4
Low level input voltage threshold VIN 0.8 V 4
High level input voltage threshold VIN 2.3 V 4
Logic 1 input bias current IIN+ 5 25 A @ VIN = 5 V @ 25C 4
Logic 0 input bias current IIN− 2 A @ VIN = 0 V @ 25C 4
Vcc UV start-up voltage threshold Vcc_stup 8 8.9 9.8 V 4
Vcc UV shut-down voltage threshold Vcc_shtdwn 7.3 8.2 9 V 4
Hysteresis on Vcc Vcc_hyst 0.3 0.7 V 4
Vboot start-up voltage threshold Vboot_stup 8 8.9 9.8 V reference to bridge pin (Vboot_stup = Vboot − Vbridge) 4
Vboot UV shut-down voltage threshold Vboot_shtdwn 7.3 8.2 9 V 4
Hysteresis on Vboot Vboot_shtdwn 0.3 0.7 V 4
Leakage current on high voltage pins to GND IHV_LEAK 5 40 A VBOOT = VBRIDGE = DRV_HI = 600 V 4
Consumption in active mode ICC1 4 5 mA Vcc = Vboot, fsw = 100 kHz and 1 nF load on both driver outputs 4
Consumption in inhibition mode ICC2 250 400 A Vcc = Vboot 4

CAD (KiCad official)

  • Symbol: NCP5104DR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncp5104dr2g-etched.step / ncp5104dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp5104dr2g.step / ncp5104dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (17 pp, sha256 65422443e7c6421d, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF