NCP4318BLCDR2G

onsemi · AC-DC Controllers And Regulators · SOIC-8

NCP4318BLCDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GATE1	output	Gate drive output for SR MOSFET1, clamped to 9 V to 12 V (10.5 V typ) for 12 V < VDD < 33 V with absolute maximum −0.3 V to 17 V, with 1.5 A peak sourcing and 4.5 A peak sinking.
2	GND	power_in	Ground reference; all voltage values in the datasheet are stated with respect to this pin.
3	VD1	input	Synchronous rectifier drain sense input for SR1, rated −4 V to 200 V absolute (−0.7 V to 180 V recommended); the IOFFSET1 current source flows out of this pin so an external series resistor can set the turn-off threshold, and it is disabled when VDD is under-voltage or switching is disabled in green mode.
4	VS1	input	Synchronous rectifier source sense input for SR1, rated −0.3 V to 5.5 V absolute (−0.3 V to 5 V recommended).
5	VS2	input	Synchronous rectifier source sense input for SR2, rated −0.3 V to 5.5 V absolute (−0.3 V to 5 V recommended).
6	VD2	input	Synchronous rectifier drain sense input for SR2, rated −4 V to 200 V absolute (−0.7 V to 180 V recommended); the IOFFSET2 current source flows out of this pin so an external series resistor can set the turn-off threshold, and it is disabled when VDD is under-voltage or switching is disabled in green mode.
7	VDD	power_in	Supply voltage, 0 V to 35 V recommended (−0.3 V to 37 V absolute maximum), with turn-on threshold 4.3 V typ and turn-off threshold 3.8 V typ.
8	GATE2	output	Gate drive output for SR MOSFET2, clamped to 9 V to 12 V (10.5 V typ) for 12 V < VDD < 33 V with absolute maximum −0.3 V to 17 V, with 1.5 A peak sourcing and 4.5 A peak sinking.

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Turn-on threshold	VDD_ON	4		4.3	V	VDD rising with 4.3 V / 1 ms	5
Turn-off threshold	VDD_OFF	3.6		3.8	V	VDD < VDD_OFF	5
SR gate enable threshold voltage	VDD_GATE_ON	6.5		7.1	V	VDD > VDD_GATE_ON	5
SR gate disable threshold voltage	VDD_GATE_OFF	5		6	V	VDD < VDD_GATE_OFF	5
Operating current	IDD_OP1		8	10	mA	fSW = 100 kHz, CGATE = 1 nF	5
Operating current in green mode	IDD_GREEN		100	210	µA	VDD = 12 V (no VD1/2 switching), GREEN1 enable at TJ = 25°C	5
Comparator input offset voltage	VOSI	-1	0	1	mV		5
Minimum off-time (BLC)	tOFF_MIN	1400	2000	2800	ns	From VD1/2 higher than VTH_HGH (ALC, BLC, ALK)	5
Turn-on propagation delay	tON_DLY		30	80	ns	From VD1/2 = −0.2 to VGATE = 1 V, when DLY_EN = 0	5
Turn-off propagation delay	tOFF_DLY		30	80	ns	From VD1/2 = 0.6 to VGATE = 5.7 V	5
Minimum SR conduction time to enable SR when DLY_EN = 0 (BLC)	tGATE_SKIP_L1		500	710	ns	Duration from turn-on trigger to VD1/2 rising higher than VTH_HGH, when DLY_EN = 0	6
Adaptive minimum on time ratio when DLY_EN = 0	KTON1	43	50	57	%	DLY_EN=0 & tSR_COND(n−1) = 8 µs	6
Minimum on-time upper limit when DLY_EN = 0	tMIN_ON_U1	4	5	6	µs	tMIN_ON_L < tMIN_ON < tMIN_ON_U, when DLY_EN = 0	6
Minimum on-time upper limit when DLY_EN = 1	tMIN_ON_U2	2	2.5	3	µs	tMIN_ON_L < tMIN_ON < tMIN_ON_U, when DLY_EN = 1	6
Adaptive SR current inversion detection window ratio when DLY_EN = 0	KINV1	43	50	57	%	KTON1 = KINV1, when DLY_EN = 0; tINV_WIN = tMIN_ON	6
Maximum SR turn-on time	tSR_MAX_ON	21	30	39	µs		6
Minimum switching frequency	fMIN	22			kHz	1/(tSR_MAX_ON_CH1 + tSR_MAX_ON_CH2)	6
Maximum of adaptive offset current (31 steps, 10 µA resolution)	IOFFSET	285	310	335	µA	VD1 = VD2 = 0	6
Non-switching period of SR gate to enter Green Mode 1 (L-version, BLC)	tGRN1_ENT	45	60	75	µs	When SR_COND1, 2 are both low for tGRN1_ENT_L, green mode1 is enabled	7
Non-switching period of SR gate to enter Green Mode 2 (L-version, BLC)	tGRN2_ENT	4.5	6	7.5	µs	When SR_COND1, 2 are both low for tGRN2_ENT_L, green mode2 is enabled	7
Drain threshold voltage for the primary shutdown protection	KSD_PRI	65	70	75	%	Detection window time ratio based on tVG1(n−1) (LLD1 = 0, tVG1(n−1) = 8 µs)	7
Gate clamping voltage	VGATE_MAX	9	10.5	12	V	12 V < VDD < 33 V, CGATE = 4.7 nF at TJ < TOTP1	8
Gate clamping voltage for adaptive gate voltage control	VGATE_MAX_7V	5	6.7	8.2	V	VDD = 12 V, CGATE = 4.7 nF	8
Adaptive gate control enabling switching period (BLC)	tHFS1_EN	4	5	6.1	µs	Time ts from VGATE1(n−1) rising edge to VGATE1(n) rising edge at TJ < TOTP1	8
Rise time	tR		50	150	ns	VDD = 12 V, CL = 3.3 nF, VGATE = 1 V to 6 V at TJ = 25°C	8
Fall time	tF		30	50	ns	VDD = 12 V, CL = 3.3 nF, VGATE = 6 V to 1 V at TJ = 25°C	8
Power Supply Input Pin Voltage	VDD	-0.3		37	V		4
Drain Sense Input Pin Voltage	VD1, VD2	-4		200	V		4
Gate Drive Output Pin Voltage	VGATE1, VGATE2	-0.3		17	V		4
Source Sense Input Pin Voltage	VS1, VS2	-0.3		5.5	V		4
Source Sense Dynamic Input Pin Voltage	VS1_DYN, VS2_DYN	-4		5.5	V	pulse width = 200 ns	4
Power Dissipation (TA = 25°C)	PD			0.625	W	TA = 25°C	4
Maximum Junction Temperature	TJ	-40		150	°C		4
Storage Temperature Range	TSTG	-60		150	°C		4
Lead Temperature (Soldering, 10 Seconds)	TL			260	°C	10 seconds	4
VDD Pin Supply Voltage to GND	VDD	0		35	V		4
Drain Sense Input Pin Voltage	VD1, VD2	-0.7		180	V		4
Source Sense Input Pin Voltage	VS1, VS2	-0.3		5	V		4
Operating Ambient Temperature	TJ	-40		125	°C		4
Startup current	IDD_START		100		µA	VDD = VDD_ON − 0.1 V	5
Operating current	IDD_OP0		6		mA	fSW = 100 kHz, CGATE = 0 nF	5
Turn-on threshold	VTH_ON		-100		mV	ROFFSET = 0 (includes comparator input offset voltage)	5
Drain voltage high detect threshold voltage	VTH_HGH		0.85		V	VD1/2 rising (ALC, BLC, AHJ, ALK)	6
Lower band of dead time regulation	tDEAD_LBAND		90		ns	From VGATE falling below VGATE_LOW (ALC, BLC, ALS, ALK)	6
Threshold voltage of current inversion detection / debounce time of SR current inversion detection	tINV		320		ns	VGATE1/2 > 4.5 V & VD1/2 > VSRC_INV for tINV (ALC, BLC, ALK)	7
Drain threshold voltage for the primary shutdown protection	VSD_PRI		150		mV	VGATE1/2 > 4.5 V & VD1/2 > VSD_PRI (ALC, BLC, ALK)	7
Drain threshold voltage to trigger abnormal VD sensing protection	VABN_VD		0.85		V	VD1/2 > VABN_VD & VGATE1/2 > 4.5 V with 100 ns delay within KSD_PRI (ALC, BLC, AHJ, ALK)	7
Over temperature protection1	TOTP1		105		°C	TJ > TOTP1 & VGATE = 6.7 V (ALC, BLC, AHJ)	7
Over temperature protection2	TOTP2		140		°C	TJ > TOTP2 & No gate output (ALC, BLC, AHJ)	7
Over temperature protection reset	TOTP_RST		80		°C	TJ < TOTP_RST, OTP1 and OTP2 are reset	7
Peak sourcing current of gate driver	ISOURCE		1.5		A		8
Peak sinking current of gate driver	ISINK		4.5		A		8
Gate driver sourcing resistance	RDRV_SOURCE		8		Ω		8
Gate driver sinking resistance	RDRV_SINK		1.5		Ω		8
Comparator input offset (turn-off threshold, minimum)	VTH_OFF_MIN		-6		mV	ROFFSET = 0 (includes comparator input offset voltage), in ALC, BLC, ALS, ALK	5
One step size of turn-off threshold voltage	VTH_OFF_STEP		4		mV	ROFFSET = 0, in ALC, BLC, AHJ	5
Maximum turn-off threshold voltage	VTH_OFF_MAX		118		mV	ROFFSET = 0, in ALC, BLC	5
Turn-off threshold voltage reset value	VTH_OFF_RST		2		mV	ROFFSET = 0, in ALC, BLC	5

CAD (KiCad official)

Symbol: NCP4318BLCDR2G
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ncp4318blcdr2g-etched.step / ncp4318blcdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp4318blcdr2g.step / ncp4318blcdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (22 pp, sha256 d8a63b4ce9ba5ac6, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# NCP4318BLCDR2G

**onsemi** · AC-DC Controllers And Regulators · SOIC-8

NCP4318BLCDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE1 | output | Gate drive output for SR MOSFET1, clamped to 9 V to 12 V (10.5 V typ) for 12 V < VDD < 33 V with absolute maximum −0.3 V to 17 V, with 1.5 A peak sourcing and 4.5 A peak sinking. |
| 2 | GND | power_in | Ground reference; all voltage values in the datasheet are stated with respect to this pin. |
| 3 | VD1 | input | Synchronous rectifier drain sense input for SR1, rated −4 V to 200 V absolute (−0.7 V to 180 V recommended); the IOFFSET1 current source flows out of this pin so an external series resistor can set the turn-off threshold, and it is disabled when VDD is under-voltage or switching is disabled in green mode. |
| 4 | VS1 | input | Synchronous rectifier source sense input for SR1, rated −0.3 V to 5.5 V absolute (−0.3 V to 5 V recommended). |
| 5 | VS2 | input | Synchronous rectifier source sense input for SR2, rated −0.3 V to 5.5 V absolute (−0.3 V to 5 V recommended). |
| 6 | VD2 | input | Synchronous rectifier drain sense input for SR2, rated −4 V to 200 V absolute (−0.7 V to 180 V recommended); the IOFFSET2 current source flows out of this pin so an external series resistor can set the turn-off threshold, and it is disabled when VDD is under-voltage or switching is disabled in green mode. |
| 7 | VDD | power_in | Supply voltage, 0 V to 35 V recommended (−0.3 V to 37 V absolute maximum), with turn-on threshold 4.3 V typ and turn-off threshold 3.8 V typ. |
| 8 | GATE2 | output | Gate drive output for SR MOSFET2, clamped to 9 V to 12 V (10.5 V typ) for 12 V < VDD < 33 V with absolute maximum −0.3 V to 17 V, with 1.5 A peak sourcing and 4.5 A peak sinking. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Turn-on threshold | VDD_ON | 4 |  | 4.3 | V | VDD rising with 4.3 V / 1 ms | 5 |
| Turn-off threshold | VDD_OFF | 3.6 |  | 3.8 | V | VDD < VDD_OFF | 5 |
| SR gate enable threshold voltage | VDD_GATE_ON | 6.5 |  | 7.1 | V | VDD > VDD_GATE_ON | 5 |
| SR gate disable threshold voltage | VDD_GATE_OFF | 5 |  | 6 | V | VDD < VDD_GATE_OFF | 5 |
| Operating current | IDD_OP1 |  | 8 | 10 | mA | fSW = 100 kHz, CGATE = 1 nF | 5 |
| Operating current in green mode | IDD_GREEN |  | 100 | 210 | µA | VDD = 12 V (no VD1/2 switching), GREEN1 enable at TJ = 25°C | 5 |
| Comparator input offset voltage | VOSI | -1 | 0 | 1 | mV |  | 5 |
| Minimum off-time (BLC) | tOFF_MIN | 1400 | 2000 | 2800 | ns | From VD1/2 higher than VTH_HGH (ALC, BLC, ALK) | 5 |
| Turn-on propagation delay | tON_DLY |  | 30 | 80 | ns | From VD1/2 = −0.2 to VGATE = 1 V, when DLY_EN = 0 | 5 |
| Turn-off propagation delay | tOFF_DLY |  | 30 | 80 | ns | From VD1/2 = 0.6 to VGATE = 5.7 V | 5 |
| Minimum SR conduction time to enable SR when DLY_EN = 0 (BLC) | tGATE_SKIP_L1 |  | 500 | 710 | ns | Duration from turn-on trigger to VD1/2 rising higher than VTH_HGH, when DLY_EN = 0 | 6 |
| Adaptive minimum on time ratio when DLY_EN = 0 | KTON1 | 43 | 50 | 57 | % | DLY_EN=0 & tSR_COND(n−1) = 8 µs | 6 |
| Minimum on-time upper limit when DLY_EN = 0 | tMIN_ON_U1 | 4 | 5 | 6 | µs | tMIN_ON_L < tMIN_ON < tMIN_ON_U, when DLY_EN = 0 | 6 |
| Minimum on-time upper limit when DLY_EN = 1 | tMIN_ON_U2 | 2 | 2.5 | 3 | µs | tMIN_ON_L < tMIN_ON < tMIN_ON_U, when DLY_EN = 1 | 6 |
| Adaptive SR current inversion detection window ratio when DLY_EN = 0 | KINV1 | 43 | 50 | 57 | % | KTON1 = KINV1, when DLY_EN = 0; tINV_WIN = tMIN_ON | 6 |
| Maximum SR turn-on time | tSR_MAX_ON | 21 | 30 | 39 | µs |  | 6 |
| Minimum switching frequency | fMIN | 22 |  |  | kHz | 1/(tSR_MAX_ON_CH1 + tSR_MAX_ON_CH2) | 6 |
| Maximum of adaptive offset current (31 steps, 10 µA resolution) | IOFFSET | 285 | 310 | 335 | µA | VD1 = VD2 = 0 | 6 |
| Non-switching period of SR gate to enter Green Mode 1 (L-version, BLC) | tGRN1_ENT | 45 | 60 | 75 | µs | When SR_COND1, 2 are both low for tGRN1_ENT_L, green mode1 is enabled | 7 |
| Non-switching period of SR gate to enter Green Mode 2 (L-version, BLC) | tGRN2_ENT | 4.5 | 6 | 7.5 | µs | When SR_COND1, 2 are both low for tGRN2_ENT_L, green mode2 is enabled | 7 |
| Drain threshold voltage for the primary shutdown protection | KSD_PRI | 65 | 70 | 75 | % | Detection window time ratio based on tVG1(n−1) (LLD1 = 0, tVG1(n−1) = 8 µs) | 7 |
| Gate clamping voltage | VGATE_MAX | 9 | 10.5 | 12 | V | 12 V < VDD < 33 V, CGATE = 4.7 nF at TJ < TOTP1 | 8 |
| Gate clamping voltage for adaptive gate voltage control | VGATE_MAX_7V | 5 | 6.7 | 8.2 | V | VDD = 12 V, CGATE = 4.7 nF | 8 |
| Adaptive gate control enabling switching period (BLC) | tHFS1_EN | 4 | 5 | 6.1 | µs | Time ts from VGATE1(n−1) rising edge to VGATE1(n) rising edge at TJ < TOTP1 | 8 |
| Rise time | tR |  | 50 | 150 | ns | VDD = 12 V, CL = 3.3 nF, VGATE = 1 V to 6 V at TJ = 25°C | 8 |
| Fall time | tF |  | 30 | 50 | ns | VDD = 12 V, CL = 3.3 nF, VGATE = 6 V to 1 V at TJ = 25°C | 8 |
| Power Supply Input Pin Voltage | VDD | -0.3 |  | 37 | V |  | 4 |
| Drain Sense Input Pin Voltage | VD1, VD2 | -4 |  | 200 | V |  | 4 |
| Gate Drive Output Pin Voltage | VGATE1, VGATE2 | -0.3 |  | 17 | V |  | 4 |
| Source Sense Input Pin Voltage | VS1, VS2 | -0.3 |  | 5.5 | V |  | 4 |
| Source Sense Dynamic Input Pin Voltage | VS1_DYN, VS2_DYN | -4 |  | 5.5 | V | pulse width = 200 ns | 4 |
| Power Dissipation (TA = 25°C) | PD |  |  | 0.625 | W | TA = 25°C | 4 |
| Maximum Junction Temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage Temperature Range | TSTG | -60 |  | 150 | °C |  | 4 |
| Lead Temperature (Soldering, 10 Seconds) | TL |  |  | 260 | °C | 10 seconds | 4 |
| VDD Pin Supply Voltage to GND | VDD | 0 |  | 35 | V |  | 4 |
| Drain Sense Input Pin Voltage | VD1, VD2 | -0.7 |  | 180 | V |  | 4 |
| Source Sense Input Pin Voltage | VS1, VS2 | -0.3 |  | 5 | V |  | 4 |
| Operating Ambient Temperature | TJ | -40 |  | 125 | °C |  | 4 |
| Startup current | IDD_START |  | 100 |  | µA | VDD = VDD_ON − 0.1 V | 5 |
| Operating current | IDD_OP0 |  | 6 |  | mA | fSW = 100 kHz, CGATE = 0 nF | 5 |
| Turn-on threshold | VTH_ON |  | -100 |  | mV | ROFFSET = 0 (includes comparator input offset voltage) | 5 |
| Drain voltage high detect threshold voltage | VTH_HGH |  | 0.85 |  | V | VD1/2 rising (ALC, BLC, AHJ, ALK) | 6 |
| Lower band of dead time regulation | tDEAD_LBAND |  | 90 |  | ns | From VGATE falling below VGATE_LOW (ALC, BLC, ALS, ALK) | 6 |
| Threshold voltage of current inversion detection / debounce time of SR current inversion detection | tINV |  | 320 |  | ns | VGATE1/2 > 4.5 V & VD1/2 > VSRC_INV for tINV (ALC, BLC, ALK) | 7 |
| Drain threshold voltage for the primary shutdown protection | VSD_PRI |  | 150 |  | mV | VGATE1/2 > 4.5 V & VD1/2 > VSD_PRI (ALC, BLC, ALK) | 7 |
| Drain threshold voltage to trigger abnormal VD sensing protection | VABN_VD |  | 0.85 |  | V | VD1/2 > VABN_VD & VGATE1/2 > 4.5 V with 100 ns delay within KSD_PRI (ALC, BLC, AHJ, ALK) | 7 |
| Over temperature protection1 | TOTP1 |  | 105 |  | °C | TJ > TOTP1 & VGATE = 6.7 V (ALC, BLC, AHJ) | 7 |
| Over temperature protection2 | TOTP2 |  | 140 |  | °C | TJ > TOTP2 & No gate output (ALC, BLC, AHJ) | 7 |
| Over temperature protection reset | TOTP_RST |  | 80 |  | °C | TJ < TOTP_RST, OTP1 and OTP2 are reset | 7 |
| Peak sourcing current of gate driver | ISOURCE |  | 1.5 |  | A |  | 8 |
| Peak sinking current of gate driver | ISINK |  | 4.5 |  | A |  | 8 |
| Gate driver sourcing resistance | RDRV_SOURCE |  | 8 |  | Ω |  | 8 |
| Gate driver sinking resistance | RDRV_SINK |  | 1.5 |  | Ω |  | 8 |
| Comparator input offset (turn-off threshold, minimum) | VTH_OFF_MIN |  | -6 |  | mV | ROFFSET = 0 (includes comparator input offset voltage), in ALC, BLC, ALS, ALK | 5 |
| One step size of turn-off threshold voltage | VTH_OFF_STEP |  | 4 |  | mV | ROFFSET = 0, in ALC, BLC, AHJ | 5 |
| Maximum turn-off threshold voltage | VTH_OFF_MAX |  | 118 |  | mV | ROFFSET = 0, in ALC, BLC | 5 |
| Turn-off threshold voltage reset value | VTH_OFF_RST |  | 2 |  | mV | ROFFSET = 0, in ALC, BLC | 5 |

## CAD (KiCad official)

- Symbol: `NCP4318BLCDR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ncp4318blcdr2g-etched.step` / `ncp4318blcdr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp4318blcdr2g.step` / `ncp4318blcdr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590197156528627712) (22 pp, sha256 `d8a63b4ce9ba5ac6`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ncp4318blcdr2g-datasheet.pdf)