component
NCP4318ALFPDR2G
Public Made by Adomby adom
onsemi Power Management - Specialized, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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NCP4318ALFPDR2G
onsemi · Power Management - Specialized · SOIC-8-EP
NCP4318ALFPDR2G from onsemi, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE1 | output | Gate drive output for SR MOSFET1; the gate output voltage is rated −0.3 V to 17 V. |
| 2 | GND | power_in | Ground reference for the device; all voltage values in the datasheet are referenced to this pin. |
| 3 | VS1 | input | Synchronous rectifier source sense input for SR1; recommended operating range is −0.3 V to 5 V, with a 200 ns dynamic limit of −4 V to 5.5 V. |
| 4 | VD1 | input | Synchronous rectifier drain sense input; the IOFFSET1 current source flows out of this pin so an external series resistor sets the turn-off threshold, and is disabled during VDD undervoltage or green-mode switching disable, with drain sense rated −4 V to 200 V (recommended −0.7 V to 180 V). |
| 5 | VS2 | input | Synchronous rectifier source sense input for SR2; recommended operating range is −0.3 V to 5 V, with a 200 ns dynamic limit of −4 V to 5.5 V. |
| 6 | VD2 | input | Synchronous rectifier drain sense input; the IOFFSET2 current source flows out of this pin so an external series resistor sets the turn-off threshold, and is disabled during VDD undervoltage or green-mode switching disable, with drain sense rated −4 V to 200 V (recommended −0.7 V to 180 V). |
| 7 | VDD | power_in | Supply voltage input; recommended operating range is 0 V to 35 V, with an absolute maximum of −0.3 V to 37 V. |
| 8 | GATE2 | output | Gate drive output for SR MOSFET2; the gate output voltage is rated −0.3 V to 17 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Pin Supply Voltage to GND | VDD | 0 | 35 | V | 4 | ||
| Drain Sense Input Pin Voltage | VD1, VD2 | -0.7 | 180 | V | 4 | ||
| Source Sense Input Pin Voltage | VS1, VS2 | -0.3 | 5 | V | 4 | ||
| Operating Junction Temperature | TJ | -40 | 125 | C | 4 | ||
| Power Supply Input Pin Voltage | VDD | -0.3 | 37 | V | 4 | ||
| Drain Sense Input Pin Voltage | VD1, VD2 | -4 | 200 | V | 4 | ||
| Gate Drive Output Pin Voltage | VGATE1, VGATE2 | -0.3 | 17 | V | 4 | ||
| Source Sense Input Pin Voltage | VS1, VS2 | -0.3 | 5.5 | V | 4 | ||
| Source Sense Input Pin Dynamic Voltage | VS1-DYN, VS2-DYN | -4 | 5.5 | V | Pulse Width = 200 ns | 4 | |
| Operating Junction Temperature (absolute maximum) | TJ | -40 | 150 | C | 4 | ||
| Storage Temperature Range | TSTG | -60 | 150 | C | 4 | ||
| Power Dissipation SOIC-8 EP | PD | 3.7 | W | TA = 25C, SOIC-8 EP (Note 3) | 4 | ||
| Lead Temperature (Soldering, 10 Seconds) | TL | 260 | C | 10 s soldering | 4 | ||
| Supply Turn-on Threshold | VDD-ON | 4 | 4.3 | V | VDD rising with 4.3 V / 1 ms | 5 | |
| Turn-off Threshold | VDD-OFF | 3.6 | 3.8 | V | VDD < VDD-OFF | 5 | |
| SR Gate Enable Threshold Voltage | VDD-GATE-ON | 6.5 | 7.1 | V | VDD > VDD-GATE-ON | 5 | |
| SR Gate Disable Threshold Voltage | VDD-GATE-OFF | 5 | 6 | V | VDD < VDD-GATE-OFF | 5 | |
| Operating Current | IDD-OP1 | 8 | 10 | mA | fSW = 100 kHz, CGATE = 1 nF | 5 | |
| Comparator Input Offset Voltage | VOSI | -1 | 0 | 1 | mV | 5 | |
| Minimum Off-time | tOFF-MIN | 1150 | 1550 | 2800 | ns | From VD1/2 higher than VTH-HGH (ALFP group value) | 5 |
| Turn-on Propagation Delay | tON-DLY | 30 | 80 | ns | From VD1/2 = -0.2 to VGATE = 1 V, when DLY_EN = 0 | 5 | |
| Turn-off Propagation Delay | tOFF-DLY | 30 | 80 | ns | Turn-off comparator delay, From VD1/2 = 0.6 to VGATE = 5.7 V | 5 | |
| Minimum SR Conduction Time to Enable SR when DLY_EN = 0 | tGATE-SKIP1 | 550 | 710 | ns | Duration from turn-on trigger to VD1/2 rising higher than VTH-HGH, when DLY_EN = 0 | 6 | |
| Upper Limit of Minimum On-time when DLY_EN = 0 | tMIN-ON-U1 | 4 | 5 | 6 | s | 200 ns < tMIN-ON < tMIN-ON-U1, DLY_EN = 0 | 6 |
| Upper Limit of Minimum On-time when DLY_EN = 1 | tMIN-ON-U2 | 2 | 2.5 | 3 | s | 200 ns < tMIN-ON < tMIN-ON-U2, DLY_EN = 1 | 6 |
| Adaptive Minimum On Time Ratio when DLY_EN = 0 | KTON1 | 29 | 34 | 39 | % | DLY_EN=0 & tSRCOND(n-1) = 8 s (ALFP/ALGP group) | 6 |
| Maximum SR Turn-on Time | tSR-MAX-ON | 21 | 30 | 39 | s | Variant ALFP (group with ALC, ALK, ALS, AHD, AHJ, BLC, ALGP) | 6 |
| Minimum Switching Frequency | fMIN | 22 | kHz | 1/(tSR-MAX-ON-CH1 + tSR-MAX-ON-CH2); variant ALFP group | 6 | ||
| Maximum Adaptive Offset Current | IOFFSET | 0 | A | VD1 = VD2 = 0; variant ALFP (IOFFSET stays at 0) | 7 | ||
| Threshold Voltage of Current Inversion Detection | VSD-PRI | 150 | mV | VGATE1/2 > 4.5 V with 200 ns delay & VD1/2 > VSD-PRI when DLY_EN = 0; 100 ns delay when DLY_EN = 1 | 7 | ||
| Debounce Time of SR Current Inversion Detection | tINV | 170 | ns | VGATE1/2 > 4.5 V & VD1/2 > VSRCINV for tINV | 7 | ||
| Lower Band of Dead Time Regulation | tDEAD-LBAND | 90 | ns | From VGATE falling below VGATE-LOW (ALFP group value) | 7 | ||
| Minimum Light Load Period for SR Gate Reset (Second Group) | tGRN2-ENT | 4.5 | 6 | 7.5 | s | When SRCOND1, 2 are both low for tGRN2-ENT, generate GREEN2 pulse | 7 |
| Primary Shutdown Detection Window Time Ratio | KSD-PRI | 65 | 70 | 75 | % | LLD = 0, tVG1(n-1) = 8 s, and K2ND-TOFF * tVG1(n-1) > tMIN-ON | 7 |
| Drain Threshold Voltage to Trigger Abnormal VD Sensing Protection | VABN-VD | 0.85 | V | VD1/2 > VABN-VD & VGATE1/2 > 4.5 V with 100 ns delay within KSD-PRI | 7 | ||
| Over Temperature Protection Reducing VGATE | TOTP1 | 130 | C | TJ > TOTP1 & VGATE = 6.7 V | 7 | ||
| Gate Clamping Voltage | VGATE-MAX | 9 | 10.5 | 12 | V | 12 V < VDD < 33 V, CGATE = 4.7 nF at TJ < TOTP1 | 8 |
| Adaptive Gate Control Enabling Switching Period | tHFS-EN | 4 | 5 | s | Time from VGATE1(n-1) rising edge to VGATE1(n) rising edge at TJ < TOTP1 (ALFP group) | 8 | |
| Peak Sourcing Current of Gate Driver | ISOURCE | 1.5 | A | 8 | |||
| Peak Sinking Current of Gate Driver | ISINK | 4.5 | A | 8 | |||
| Gate Driver Sourcing Resistance | RDRV-SOURCE | 8 | Ω | 8 | |||
| Gate Driver Sinking Resistance | RDRV-SINK | 1.5 | Ω | 8 | |||
| Rise Time | tR | 50 | 150 | ns | VDD = 12 V, CGATE = 3.3 nF, VGATE = 1 to 6 V at TJ = 25C | 8 | |
| Fall Time | tF | 30 | 50 | ns | VDD = 12 V, CGATE = 3.3 nF, VGATE = 6 to 1 V at TJ = 25C | 8 | |
| Start-up Current | IDD-START | 100 | A | VDD = VDD-ON - 0.1 V | 5 | ||
| Operating Current fSW = 100 kHz, CGATE = 0 nF | IDD-OP0 | 6 | mA | fSW = 100 kHz, CGATE = 0 nF | 5 | ||
| Drain Pin Leakage Current | IDRAIN-LKG | 1 | A | VD1/2 = 200 V | 5 | ||
| Turn-on Threshold | VTH-ON | -100 | mV | ROFFSET = 0 (includes comparator input offset voltage) | 5 | ||
| Turn-on De-bounce Time When Additional Turn-on Delay is Enabled | tON-DLY2 | 240 | ns | From VD1/2 = -0.2 to VGATE = 1 V, when DLY_EN = 1 | 5 | ||
| Minimum Turn-off Threshold Voltage | VTH-OFF-MIN | -14 | mV | ROFFSET = 0 (includes comparator input offset voltage) | 5 | ||
| Step Size of Adaptive Turn-off Threshold Voltage | VTH-OFF-STEP | 4 | mV | ROFFSET = 0 | 5 | ||
| Maximum Turn-off Threshold Voltage | VTH-OFF-MAX | 110 | mV | ROFFSET = 0 | 5 | ||
| Reset Value of Turn-off Threshold Voltage | VTH-OFF-RST | -6 | mV | ROFFSET = 0 | 5 | ||
| Ratio of Second-step VTH-OFF to VTH-OFF | K2ND-VOFF | 60 | % | LLD = 0 | 6 | ||
| Effective On-time Duration Ratio for the Second Step VTH-OFF | K2ND-TOFF | 70 | % | LLD = 0, tVG1(n-1) = 8 s, and K2ND-TOFF * tVG1(n-1) > tMIN-ON | 6 | ||
| Drain Voltage High Detect Threshold Voltage | VTH-HGH | 0.85 | V | VD1/2 rising | 6 | ||
| Minimum SR Conduction Time to Enable SR when DLY_EN = 1 | tGATE-SKIP2 | 510 | ns | Duration from turn-on trigger to VD1/2 rising higher than VTH-HGH, when DLY_EN = 1 | 6 | ||
| Adaptive Minimum On Time Ratio when DLY_EN = 1 | KTON2 | 17 | % | DLY_EN = 1 & tSRCOND(n-1) = 8 s (ALFP/ALGP group) | 6 |
CAD (KiCad official)
- Symbol:
NCP4318ALFPDR2G - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
ncp4318alfpdr2g-etched.step/ncp4318alfpdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp4318alfpdr2g.step/ncp4318alfpdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (26 pp, sha256
907d01048d8bb997, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).