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NCP4304BDR2G

Public Made by Adom

by adom

onsemi Pre-ordered transistors, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

NCP4304BDR2G

onsemi · Pre-ordered transistors · SOIC-8

NCP4304BDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Supply terminal of the controller, accepts up to 30 V continuously.
2 MIN_TOFF passive Adjusts the minimum off time period by connecting a resistor to ground.
3 MIN_TON passive Adjusts the minimum on time period by connecting a resistor to ground.
4 TRIG/DIS input Ultrafast forced reset input that turns off the SR MOSFET in CCM applications, and activates sleep mode if pulled up for more than 100 µs.
5 CS input Current sense input of the SR MOSFET detecting current through the MOSFET and/or its body diode, with a basic turn-off threshold of 0 mV that a series resistor can modify (rated -4 to 200 V dc).
6 COMP passive Kelvin connection to the auxiliary compensation inductance; connect directly to the GND pin if package parasitic inductance compensation is not used.
7 GND power_in IC ground for the SR MOSFET driver, VCC decoupling capacitor, MIN_TON/MIN_TOFF resistors and trigger input, wired directly to the SR MOSFET source by Kelvin connection.
8 DRV output Gate driver output for the SR MOSFET (5 A sink/2.5 A source peak, 6 V clamp on the B version).

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Transistors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IC Supply Voltage VCC -0.3 30 V 4
Driver Output Voltage VDRV -0.3 17 V 4
Current Sense Input dc Voltage VCS -4 200 V 4
Current Sense Input Dynamic Voltage VCsdyn -10 200 V tpw = 200 ns 4
Trigger Input Voltage VTRIG/DIS -0.3 10 V 4
MIN_TON and MIN_TOFF Input Voltage VMIN_TON, VMIN_TOFF -0.3 10 V 4
MIN_TON and MIN_TOFF Current IMIN_TON, IMIN_TOFF -10 10 mA 4
Static Voltage Difference between COMP and GND VCOMP -3 10 V Internally clamped 4
Dynamic Voltage Difference between COMP and GND VCOMP_dyn -10 10 V tpw = 200 ns 4
Current into COMP Pin ICOMP -5 5 mA 4
Maximum Junction Temperature TJmax 150 °C 4
Storage Temperature Range TSmax -60 150 °C 4
Lead Temperature (Soldering, 10 s) TLmax 300 °C 4
Thermal Resistance Junction-to-Air, SOIC A/B Versions RθJA 180 °C/W SOIC 4
ESD Capability, Human Body Model 2 kV except pin 5 (650 V per JESD22-A114E) 4
ESD Capability, Machine Model 200 V JESD22-A115-A 4
Turn-on threshold level VCC_on 9.3 9.9 10.5 V VCC going up 4
Minimum operating voltage after turn-on VCC_off 8.3 8.9 9.5 V VCC going down 4
VCC hysteresis VCC_hyste 0.6 1 1.4 V 4
Internal IC consumption (B version) ICC1_B 4 6.2 mA no output load on pin 8, fSW = 500 kHz, ton_min = 500 ns, toff_min = 620 ns 4
Internal IC consumption (B version) ICC2_B 6.5 9 mA CDRV = 1 nF on pin 8, fSW = 400 kHz, ton_min = 500 ns, toff_min = 620 ns 4
Internal IC consumption (B version) ICC3_B 35 65 mA CDRV = 10 nF on pin 8, fSW = 400 kHz, ton_min = 500 ns, toff_min = 620 ns 4
Startup current consumption ICC_StartUp 35 75 µA VCC = VCC_on − 0.1 V, no switching at CS pin 4
Current consumption during disable mode ICC_Disable_1 45 90 µA No switching at CS pin, VTRIG/DIS = 5 V 4
Current consumption during disable mode (CS switching) ICC_Disable_2 200 330 µA fSW = 500 kHz, VCS_high = 4 V, VCS_low = −1 V, VTRIG/DIS = 5 V 4
Driver source resistance Roh 1.8 7 Ω Guaranteed by design 4
Driver sink resistance Rol 1 2 Ω 4
Output voltage rise-time for B version tr_B 80 ns CDRV = 10 nF 4
Output voltage fall-time for B version tf_B 35 ns CDRV = 10 nF 4
Minimum drive output voltage for B version VDRV(min_B) 4.5 V VCC = VCC_off + 200 mV 5
Driver clamp voltage for B version VDRV(CLMP_B) 5 6 8 V 12 < VCC < 28, CDRV = 1 nF 5
Output source peak current IDRV_pk(source) 2.5 A 5
Output sink peak current IDRV_pk(sink) 5 A 5
Propagation delay CS input to DRV turn on tpd_on 60 90 ns VCS goes down from 4 V to −1 V, tf_CS = 5 ns, COMP pin connected to GND 5
Propagation delay CS input to DRV turn off tpd_off 40 55 ns VCS goes up from −1 V to 4 V, tr_CS = 5 ns, COMP pin connected to GND 5
Current sense input current source Ishift_CS 95 100 105 µA VCS = 0 V 5
Current sense pin turn-on input threshold voltage Vth_cs_on -120 -85 -50 mV 5
Current sense pin turn-off threshold voltage Vth_cs_off -1 0 mV COMP pin connected to GND 5
Current Sense input leakage current ICS_Leakage 1 µA VCS = 200 V 5
Minimum trigger pulse width tTRIG/DIS_pw_min 30 ns Guaranteed by design 5
Trigger input threshold voltage VTRIG/DIS 1.5 2.5 V VTRIG/DIS goes up 5
Propagation delay from trigger input to DRV output tp_TRIG/DIS 13 30 ns VTRIG/DIS goes up from 0 to 5 V, tr_TRIG/DIS = 5 ns 5
Light load turn off filter duration tTRIG/DIS_light_load 70 100 130 µs 5
IC operation recovery time leaving light load disable mode tTRIG/DIS_light_load_rec. 10 µs VTRIG/DIS goes down from 5 to 0 V, tf_TRIG/DIS = 5 ns 5
Minimum toff period toff_min 560 600 690 ns RMIN_TOFF = 0 5
Minimum ton period ton_min 0.9 1 1.1 µs RMIN_TON = 10 k 5
Minimum toff period toff_min 0.9 1 1.1 µs RMIN_TOFF = 10 k 5
Minimum ton period ton_min 8.64 9.6 10.56 µs RMIN_TON = 100 k (Note 2) 5
Minimum toff period toff_min 8.55 9.5 10.45 µs RMIN_TOFF = 100 k (Note 2) 5
Blanking time of trigger during DRV rising edge tTRIG/DIS_blank 120 ns VCS < Vth_cs_on, single pulse on trigger tTRIG/DIS_pw = 50 ns 5
Trigger input pull down current ITRIG/DIS 10 µA VTRIG/DIS = 5 V 5
Minimum ton period ton_min 130 ns RMIN_TON = 0 5
Minimum ton period ton_min 4.8 µs RMIN_TON = 50 k 5
Minimum toff period toff_min 4.8 µs RMIN_TOFF = 50 k 5

CAD (KiCad official)

  • Symbol: NCP4304BDR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncp4304bdr2g-etched.step / ncp4304bdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp4304bdr2g.step / ncp4304bdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (34 pp, sha256 9d2c4dbde349a499, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF