component
NCP4303ADR2G
Public Made by Adomby adom
onsemi AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NCP4303ADR2G
onsemi · AC-DC Controllers And Regulators · SOIC-8
NCP4303ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supplies the driver VCC supply terminal of the controller and accepts up to 30 V continuously. |
| 2 | Min_toff | input | Adjusts the minimum off time period through a resistor connected to ground, with the Min_Toff input voltage limited to −0.3 to 10 V. |
| 3 | Min_ton | input | Adjusts the minimum on time period through a resistor connected to ground, with the Min_Ton input voltage limited to −0.3 to 10 V. |
| 4 | TRIG/Disable | input | Ultrafast turn-off forced reset input that activates sleep mode if pulled up for more than 100 s as printed, and should be connected to GND when not used; trigger input voltage is limited to −0.3 to 10 V. |
| 5 | CS | input | Current sense input that detects current through the SR MOSFET and/or its body diode with a basic turn-off threshold of 0 mV, where a series resistor can modify the threshold; DC input voltage is limited to −4 to 200 V. |
| 6 | COMP | passive | Kelvin connection to the auxiliary compensation inductance, which should be connected directly to GND if SR MOSFET package parasitic inductance compensation is not used; static GND-to-COMP voltage difference is limited to −3 to 10 V. |
| 7 | GND | power_in | IC ground for the SR MOSFET driver, VCC decoupling capacitor, minimum on/off time resistors and trigger input, to be wired directly to the SR MOSFET source using a Kelvin connection. |
| 8 | DRV | output | Gate driver output for the SR MOSFET, with driver output voltage limited to −0.3 to 17 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Turn-on threshold level (VCC going up) | VCC_on | 9.3 | 9.9 | 10.5 | V | 5 | |
| Minimum operating voltage after turn-on (VCC going down) | VCC_off | 8.3 | 8.9 | 9.5 | V | 5 | |
| VCC hysteresis | VCC_hyste | 0.8 | 1 | 1.3 | V | 5 | |
| Startup current consumption and consumption during light load (disable) mode | ICC_SDM | 390 | 550 | A | VCC = VCC_on − 0.1 V; Fsw = 500 kHz, Vtrig = 5 V | 5 | |
| Startup current consumption and consumption during light load (disable) mode (Vcs = 0 V) | ICC_SDM NS | 280 | 450 | A | VCC = VCC_on − 0.1 V; Vcs = 0 V, Vtrig = 5 V | 5 | |
| Driver high level output voltage on A version | VDRV(H)_A | 10 | V | Cload = 1 nF | 5 | ||
| Driver high level output voltage on A version | VDRV(H)_A | 11.8 | V | Cload = 10 nF | 5 | ||
| Driver high level output voltage on B version | VDRV(H)_B | 5 | V | Cload = 1 nF | 5 | ||
| Driver high level output voltage on B version | VDRV(H)_B | 6 | V | Cload = 10 nF | 5 | ||
| Minimum drive output voltage for A version | VDRV(min_A) | 8.3 | V | VCC = VCC_off + 200 mV | 5 | ||
| Minimum drive output voltage for B version | VDRV(min_B) | 4.5 | V | VCC = VCC_off + 200 mV | 5 | ||
| Driver clamp voltage for A version | VDRV(CLMP_A) | 12 | 16 | V | 12 V < VCC < 28 V, minimum Cload = 1 nF | 5 | |
| Driver clamp voltage for B version | VDRV(CLMP_B) | 7 | 8.3 | V | 12 V < VCC < 28 V, minimum Cload = 1 nF | 5 | |
| Driver source resistance | Roh | 1.8 | 7 | Note 3 (guaranteed by design) | 5 | ||
| Driver sink resistance | Rol | 1 | 2 | 5 | |||
| Total propagation delay from CS input to DRV output turn on | Tpd_on | 60 | 90 | ns | VCS goes down from 4 V to −1 V, tf_CS = 5 ns, COMP pin connected to GND | 5 | |
| Total propagation delay from CS input to DRV output turn off | Tpd_off | 40 | 55 | ns | VCS goes up from −1 V to 4 V, tr_CS = 5 ns, COMP pin connected to GND (Note 3) | 5 | |
| Current sense input current source | Ishift_CS | 95 | 100 | 105 | A | VCS = 0 V | 5 |
| Turn on current sense input threshold voltage | Vth_cs_on | -120 | -85 | -50 | mV | 5 | |
| Current sense pin turn off threshold voltage | Vth_cs_off | -1 | 0 | mV | COMP pin connected to GND (Note 3) | 5 | |
| CS input leakage current | ICS_Leakage | 1 | A | VCS = 200 Vdc | 6 | ||
| Minimum trigger pulse duration | Ttrig_pw | 30 | ns | 6 | |||
| Trigger input threshold voltage (Vtrig goes up) | Vtrig | 1.5 | 2.5 | V | Vtrig goes up | 6 | |
| Propagation delay from trigger input to the DRV output | tp_trig | 30 | ns | Vtrig goes up from 0 to 5 V, tr_trig = 5 ns | 6 | ||
| IC operation recovery time when leaving light load disable mode | ttrig_light_load_rec | 550 | ns | Vtrig goes down from 5 to 0 V, tf_trig = 5 ns | 6 | ||
| Minimum Ton period | Ton_min | 0.9 | 1 | 1.1 | s | RT_on_min = 10 k | 6 |
| Minimum Toff period | Toff_min | 0.9 | 1 | 1.1 | s | RT_off_min = 10 k | 6 |
| IC supply voltage | VCC | -0.3 | 30 | V | 4 | ||
| Driver output voltage | VDRV | -0.3 | 17 | V | 4 | ||
| Current sense input dc voltage | VCS | -4 | 200 | V | 4 | ||
| Current sense input dynamic voltage | VCsdyn | -10 | 200 | V | tpw = 200 ns | 4 | |
| Trigger input voltage | VTRIG | -0.3 | 10 | V | 4 | ||
| Min_Ton and Min_Toff input voltage | VMin_ton, VMin_toff | -0.3 | 10 | V | 4 | ||
| Min_Ton and Min_Toff current | I_Min_Toff, I_Min_Toff | -10 | 10 | mA | 4 | ||
| Static voltage difference between GND and COMP pins (internally clamped) | VGND−COMP | -3 | 10 | V | 4 | ||
| Dynamic voltage difference between GND and COMP pins | VGND−COMP_dyn | -10 | 10 | V | tpw = 200 ns | 4 | |
| Current into COMP pin | ICOMP | -5 | 5 | mA | 4 | ||
| Maximum junction temperature | TJmax | 150 | °C | 4 | |||
| Storage temperature range | TSmax | -60 | 150 | °C | 4 | ||
| Lead temperature (Soldering, 10 s) | TLmax | 300 | °C | Soldering, 10 s | 4 | ||
| ESD Capability, Human Body Model | HBM ESD | 2 | kV | except pin VCS (pin 5); pin 5 HBM is 650 V | 4 | ||
| ESD Capability, Machine Model | MM ESD | 200 | V | 4 | |||
| ESD Capability, Charged Device Model | CDM ESD | 250 | V | 4 | |||
| Thermal Resistance Junction-to-Air, SOIC version, A/B version | RJA | 180 | °C/W | SOIC version | 4 |
CAD (KiCad official)
- Symbol:
NCP4303ADR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp4303adr2g-etched.step/ncp4303adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp4303adr2g.step/ncp4303adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (31 pp, sha256
65aea68e064b61b2, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NCP4303ADR2G
**onsemi** · AC-DC Controllers And Regulators · SOIC-8
NCP4303ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supplies the driver VCC supply terminal of the controller and accepts up to 30 V continuously. |
| 2 | Min_toff | input | Adjusts the minimum off time period through a resistor connected to ground, with the Min_Toff input voltage limited to −0.3 to 10 V. |
| 3 | Min_ton | input | Adjusts the minimum on time period through a resistor connected to ground, with the Min_Ton input voltage limited to −0.3 to 10 V. |
| 4 | TRIG/Disable | input | Ultrafast turn-off forced reset input that activates sleep mode if pulled up for more than 100 s as printed, and should be connected to GND when not used; trigger input voltage is limited to −0.3 to 10 V. |
| 5 | CS | input | Current sense input that detects current through the SR MOSFET and/or its body diode with a basic turn-off threshold of 0 mV, where a series resistor can modify the threshold; DC input voltage is limited to −4 to 200 V. |
| 6 | COMP | passive | Kelvin connection to the auxiliary compensation inductance, which should be connected directly to GND if SR MOSFET package parasitic inductance compensation is not used; static GND-to-COMP voltage difference is limited to −3 to 10 V. |
| 7 | GND | power_in | IC ground for the SR MOSFET driver, VCC decoupling capacitor, minimum on/off time resistors and trigger input, to be wired directly to the SR MOSFET source using a Kelvin connection. |
| 8 | DRV | output | Gate driver output for the SR MOSFET, with driver output voltage limited to −0.3 to 17 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Turn-on threshold level (VCC going up) | VCC_on | 9.3 | 9.9 | 10.5 | V | | 5 |
| Minimum operating voltage after turn-on (VCC going down) | VCC_off | 8.3 | 8.9 | 9.5 | V | | 5 |
| VCC hysteresis | VCC_hyste | 0.8 | 1 | 1.3 | V | | 5 |
| Startup current consumption and consumption during light load (disable) mode | ICC_SDM | | 390 | 550 | A | VCC = VCC_on − 0.1 V; Fsw = 500 kHz, Vtrig = 5 V | 5 |
| Startup current consumption and consumption during light load (disable) mode (Vcs = 0 V) | ICC_SDM NS | | 280 | 450 | A | VCC = VCC_on − 0.1 V; Vcs = 0 V, Vtrig = 5 V | 5 |
| Driver high level output voltage on A version | VDRV(H)_A | 10 | | | V | Cload = 1 nF | 5 |
| Driver high level output voltage on A version | VDRV(H)_A | 11.8 | | | V | Cload = 10 nF | 5 |
| Driver high level output voltage on B version | VDRV(H)_B | 5 | | | V | Cload = 1 nF | 5 |
| Driver high level output voltage on B version | VDRV(H)_B | 6 | | | V | Cload = 10 nF | 5 |
| Minimum drive output voltage for A version | VDRV(min_A) | 8.3 | | | V | VCC = VCC_off + 200 mV | 5 |
| Minimum drive output voltage for B version | VDRV(min_B) | 4.5 | | | V | VCC = VCC_off + 200 mV | 5 |
| Driver clamp voltage for A version | VDRV(CLMP_A) | | 12 | 16 | V | 12 V < VCC < 28 V, minimum Cload = 1 nF | 5 |
| Driver clamp voltage for B version | VDRV(CLMP_B) | | 7 | 8.3 | V | 12 V < VCC < 28 V, minimum Cload = 1 nF | 5 |
| Driver source resistance | Roh | | 1.8 | 7 | | Note 3 (guaranteed by design) | 5 |
| Driver sink resistance | Rol | | 1 | 2 | | | 5 |
| Total propagation delay from CS input to DRV output turn on | Tpd_on | | 60 | 90 | ns | VCS goes down from 4 V to −1 V, tf_CS = 5 ns, COMP pin connected to GND | 5 |
| Total propagation delay from CS input to DRV output turn off | Tpd_off | | 40 | 55 | ns | VCS goes up from −1 V to 4 V, tr_CS = 5 ns, COMP pin connected to GND (Note 3) | 5 |
| Current sense input current source | Ishift_CS | 95 | 100 | 105 | A | VCS = 0 V | 5 |
| Turn on current sense input threshold voltage | Vth_cs_on | -120 | -85 | -50 | mV | | 5 |
| Current sense pin turn off threshold voltage | Vth_cs_off | -1 | | 0 | mV | COMP pin connected to GND (Note 3) | 5 |
| CS input leakage current | ICS_Leakage | | | 1 | A | VCS = 200 Vdc | 6 |
| Minimum trigger pulse duration | Ttrig_pw | 30 | | | ns | | 6 |
| Trigger input threshold voltage (Vtrig goes up) | Vtrig | 1.5 | | 2.5 | V | Vtrig goes up | 6 |
| Propagation delay from trigger input to the DRV output | tp_trig | | | 30 | ns | Vtrig goes up from 0 to 5 V, tr_trig = 5 ns | 6 |
| IC operation recovery time when leaving light load disable mode | ttrig_light_load_rec | | | 550 | ns | Vtrig goes down from 5 to 0 V, tf_trig = 5 ns | 6 |
| Minimum Ton period | Ton_min | 0.9 | 1 | 1.1 | s | RT_on_min = 10 k | 6 |
| Minimum Toff period | Toff_min | 0.9 | 1 | 1.1 | s | RT_off_min = 10 k | 6 |
| IC supply voltage | VCC | -0.3 | | 30 | V | | 4 |
| Driver output voltage | VDRV | -0.3 | | 17 | V | | 4 |
| Current sense input dc voltage | VCS | -4 | | 200 | V | | 4 |
| Current sense input dynamic voltage | VCsdyn | -10 | | 200 | V | tpw = 200 ns | 4 |
| Trigger input voltage | VTRIG | -0.3 | | 10 | V | | 4 |
| Min_Ton and Min_Toff input voltage | VMin_ton, VMin_toff | -0.3 | | 10 | V | | 4 |
| Min_Ton and Min_Toff current | I_Min_Toff, I_Min_Toff | -10 | | 10 | mA | | 4 |
| Static voltage difference between GND and COMP pins (internally clamped) | VGND−COMP | -3 | | 10 | V | | 4 |
| Dynamic voltage difference between GND and COMP pins | VGND−COMP_dyn | -10 | | 10 | V | tpw = 200 ns | 4 |
| Current into COMP pin | ICOMP | -5 | | 5 | mA | | 4 |
| Maximum junction temperature | TJmax | | | 150 | °C | | 4 |
| Storage temperature range | TSmax | -60 | | 150 | °C | | 4 |
| Lead temperature (Soldering, 10 s) | TLmax | | | 300 | °C | Soldering, 10 s | 4 |
| ESD Capability, Human Body Model | HBM ESD | | | 2 | kV | except pin VCS (pin 5); pin 5 HBM is 650 V | 4 |
| ESD Capability, Machine Model | MM ESD | | | 200 | V | | 4 |
| ESD Capability, Charged Device Model | CDM ESD | | | 250 | V | | 4 |
| Thermal Resistance Junction-to-Air, SOIC version, A/B version | RJA | | 180 | | °C/W | SOIC version | 4 |
## CAD (KiCad official)
- Symbol: `NCP4303ADR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ncp4303adr2g-etched.step` / `ncp4303adr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp4303adr2g.step` / `ncp4303adr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586188595581358080) (31 pp, sha256 `65aea68e064b61b2`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ncp4303adr2g-datasheet.pdf)