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NCP3232NMNTXG

onsemi · DC-DC Converters · QFN-40-EP(6x6)

NCP3232NMNTXG from onsemi, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SS	passive	A capacitor from this pin to GND sets the soft-start ramp time.
2	FB	input	Output voltage feedback input to the error amplifier, referenced to the internal 0.6 V reference.
3	COMP	output	Output of the error amplifier, which requires a type III compensation network.
4	ISET	passive	A resistor from this pin to ground sets the over-current protection (OCP) threshold; if RSET is not connected, OCP switches to a fixed 300 mV threshold.
5	AGND	power_in	Analog ground.
6	OTS	input	Negative input of the internal thermal comparator with a 0.6 V rising threshold; tie to ground if not used.
7	PG	output	Power good indicator of the output voltage; open-drain output that must be connected to VDD through an external resistor.
8	VIN	power_in	Connected to the internal power NMOS switch; the pin has high di/dt edges and must be decoupled to ground close to the pin.
9	VIN	power_in	Connected to the internal power NMOS switch; the pin has high di/dt edges and must be decoupled to ground close to the pin.
10	VIN	power_in	Connected to the internal power NMOS switch; the pin has high di/dt edges and must be decoupled to ground close to the pin.
11	VIN	power_in	Connected to the internal power NMOS switch; the pin has high di/dt edges and must be decoupled to ground close to the pin.
12	VIN	power_in	Connected to the internal power NMOS switch; the pin has high di/dt edges and must be decoupled to ground close to the pin.
13	VIN	power_in	Connected to the internal power NMOS switch; the pin has high di/dt edges and must be decoupled to ground close to the pin.
14	VIN	power_in	Connected to the internal power NMOS switch; the pin has high di/dt edges and must be decoupled to ground close to the pin.
15	VSWH	passive	Drain and source connection of the internal NMOS switches; the inductor drives this pin below ground at switch-off with high dv/dt.
16	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
17	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
18	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
19	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
20	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
21	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
22	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
23	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
24	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
25	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
26	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
27	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
28	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
29	VSWH	passive	Drain and source connection of the internal NMOS switches; the inductor drives this pin below ground at switch-off with high dv/dt.
30	VSWH	passive	Drain and source connection of the internal NMOS switches; the inductor drives this pin below ground at switch-off with high dv/dt.
31	VSWH	passive	Drain and source connection of the internal NMOS switches; the inductor drives this pin below ground at switch-off with high dv/dt.
32	VSWH	passive	Drain and source connection of the internal NMOS switches; the inductor drives this pin below ground at switch-off with high dv/dt.
33	VSWH	passive	Drain and source connection of the internal NMOS switches; the inductor drives this pin below ground at switch-off with high dv/dt.
34	VSWH	passive	Drain and source connection of the internal NMOS switches; the inductor drives this pin below ground at switch-off with high dv/dt.
35	VSW	passive	Connection to the switch node between the top and bottom MOSFETs; return path of the high-side gate driver and sense point for low-side OCP.
36	BST	power_in	Top gate driver input supply; a bootstrap capacitor connects between SWN and this pin.
37	PGND	power_in	Ground reference and high-current return path for the bottom gate driver and low-side NMOS.
38	VB	power_out	Internal LDO output and input supply for the charge pump; connect a minimum of 4.7 uF ceramic capacitor from this pin to ground.
39	VCC	power_in	Input supply for the IC; this pin must be connected to VIN.
40	EN	input	Logic enable for the switcher with an internal pull-up that enables the device automatically when floating; drive high to turn on or low to turn off.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	QFN-40-EP(6x6)
Category	Power Management (PMIC)
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power Supply to GND	VIN, VCC	-0.3		23	V		4
VSW to GND	VSWH, VSW	-0.6		30	V	DC	4
VSW to GND (transient)	VSWH, VSW	-5		35	V	min: t < 100 ns; max: t < 50 ns	4
BST to GND	BST	-0.6		35	V	DC	4
BST to GND (transient)	BST			40	V	t < 50 ns	4
BST to VSW		-0.3		6.5	V		4
VIN to VSW		-0.3		28	V	VIN = VCC, DC	4
VIN to VSW (transient)		-4			V	t < 50 ns	4
All other pins		-0.3		6	V		4
Operating Ambient Temperature Range	TA	-40		125	°C		4
Operating Junction Temperature Range	TJ	-40		125	°C		4
Maximum Junction Temperature	TJ(MAX)			150	°C		4
Storage Temperature Range	Tstg	-55		150	°C		4
VIN/VCC Operation Voltage	VIN/VCC	4.5		21	V		5
VB UVLO Threshold (Rising)		4.1	4.2	4.3	V		5
VB UVLO Threshold (Falling)		3.4	3.6	3.8	V		5
VB Output Voltage	VB	4.9	5.15	5.45	V	VCC = 6 V, 0 ≤ IB ≤ 40 mA	5
VB Dropout Voltage			36	110	mV	IB = 25 mA, VCC = 4.5 V	5
VCC Quiescent Current			4.7	6.4	mA	EN = H, COMP = H, no switching; PG open; no switching	5
Shutdown Supply Current			100	140	µA	EN = 0; VCC = 21 V; PG open	5
Shutdown Supply Current			55	75	µA	EN = 0; VCC = 4.5 V; PG open	5
FB Input Voltage	VFB	0.597	0.6	0.603	V	0°C < TJ < 70°C, 4.5 V ≤ VCC ≤ 21 V	5
FB Input Voltage	VFB	0.594	0.6	0.606	V	−40°C < TJ < 125°C; 4.5 V ≤ VCC ≤ 21 V	5
Open Loop DC Gain	GBD	60	85		dB		5
Open Loop Unity Gain Bandwidth	F0dB,EA	24			MHz		5
Low-side ISET Current Source	LS_ISET	30.5	33	35.5	µA	Sourced from ISET pin, before SS, TJ = 25°C	5
Low-side Programmable OCP Range				600	mV	Guaranteed by characterization; printed as < 600 mV	5
Maximum duty cycle				92	%	fsw = 500 kHz, VFB = 0 V, 4.5 V < VCC < 21 V	5
Oscillator Frequency Range	fsw	450	500	550	kHz	fsw = 500 kHz, 4.5 V < VCC < 21 V	6
Enable Threshold Voltage	VEN	1.11	1.2	1.29	V	VEN rising	6
SS Source Current	ISS	2.15	2.5	2.8	µA		6
Power Good Sink Current		10	20	30	mA	PG = 0.15 V	6
Output Overvoltage Rising		665	675	685	mV		6
Output Under-Voltage Trip Threshold		500	525	550	mV		6
High-side on Resistance	RDSONH		6.5	10	mΩ	VIN/VCC = 5 V, ID = 2 A	6
Low-side on Resistance	RDSONL		2.9	5.2	mΩ	VIN/VCC = 5 V, ID = 2 A	6
OTS comparator reference voltage (Rising Threshold)		0.59	0.6	0.61	V		6
Feedback Input Bias Current	IFB		75		nA	VFB = 0.6 V	5
Open Loop Phase Margin			60		°		5
Slew Rate			2.5		V/µs	COMP pin to GND = 10 pF	5
COMP Clamp Voltage, High			3.4		V		5
COMP Clamp Voltage, Low			0.465		V		5
Output Source Current			15		mA	VFB = 0 V	5
Output Sink Current			20		mA	VFB = 1 V	5
Low-side ISET Current Source Temperature Coefficient	TC_LS_ISET		0.31		%/°C		5
Low-side OCP Switch-over Threshold			600		mV	Guaranteed by design	5
Low-side Fixed OCP Threshold	LS_OCPth		300		mV	Guaranteed by design	5
LS OCP Blanking time	LS_Tblnk		150		ns	Guaranteed by design	5
PWM Ramp Offset			0.64		V		5
Hiccup Timer	thiccup		4		ms	tss < 1 ms, fsw = 500 kHz	6
EN Input Operating Range			5.5		V		6
Enable Pull-up Current			2		µA		6
SS Start Delay	tSSD		1.33		ms		6
Output Overvoltage Fault Blanking Time			20		µs	Guaranteed by design	6
Under-voltage Protection Blanking Time			20		µs		6
VFBOOT	VFBOOT		0.28		V	IBOOT = 2 mA	6
Thermal Shutdown Threshold			150		°C	Guaranteed by characterization	6
HS FET Junction-to-case thermal resistance	RJC-HS		1.3		°C/W	Note 1 (cold plate test on exposed pad)	4
LS FET Junction-to-case thermal resistance	RJC-LS		0.6		°C/W	Note 1 (cold plate test on exposed pad)	4
Junction-to-ambient thermal resistance	RJA		35		°C/W		4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		and precision reference allow the user to implement this pin as an adjustable UVLO circuit. EP41 GND Exposed Pad. Connect GND to a large copper plane at ground potential to improve thermal dissipatio	3

CAD (KiCad official)

Symbol: NCP3232NMNTXG
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
3D model files: ncp3232nmntxg-etched.step / ncp3232nmntxg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp3232nmntxg.step / ncp3232nmntxg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (15 pp, sha256 1a074d95dd477d4c, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF