component
NCP3135MNTXG
Public Made by Adomby adom
onsemi DC-DC Converters, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NCP3135MNTXG
onsemi · DC-DC Converters · QFN-16-EP(3x3)
NCP3135MNTXG from onsemi, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Logic control to enable the switcher, internally pulled up to VDD with a 1.35 M resistor. |
| 2 | NC | unconnected | Not connected. |
| 3 | PGD | output | Open-drain power good output, which the Power Good Monitor section describes as a 5 mA pull-down output. |
| 4 | VBST | power_out | Gate drive voltage for the high-side FET; connect a capacitor from this pin to SW. |
| 5 | SW | output | Switch node between the high-side MOSFET and the low-side MOSFET. |
| 6 | SW | output | Switch node between the high-side MOSFET and the low-side MOSFET. |
| 7 | SW | output | Switch node between the high-side MOSFET and the low-side MOSFET. |
| 8 | PS | input | Mode configuration pin with a 10 µA pull-up: pulled high or floating selects Forced Continuous Conduction Mode, and a resistor equal to or lower than 174 k to GND selects Automatic CCM/DCM. |
| 9 | COMP | output | Output of the error amplifier. |
| 10 | FB | input | Feedback pin; connect to a resistor divider to set the desired output voltage. |
| 11 | AGND | power_in | Analog ground, to be separated from power ground and joined to it at a single point per the layout guidelines. |
| 12 | VDD | power_in | Power supply input for the control circuitry. |
| 13 | VIN | power_in | Power input for power conversion and gate driver supply. |
| 14 | VIN | power_in | Power input for power conversion and gate driver supply. |
| 15 | PGND | power_in | Power ground. |
| 16 | PGND | power_in | Power ground. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | QFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN, VDD, PS, EN | -0.3 | 6.5 | V | 4 | ||
| VBST voltage | VBST | -0.3 | 17 | V | 4 | ||
| VBST voltage with respect to SW | VBST (with respect to SW) | -0.3 | 6.5 | V | 4 | ||
| FB voltage | FB | -0.3 | 3.7 | V | 4 | ||
| Output voltage range SW DC | SW | -1 | 6.5 | V | DC | 4 | |
| Output voltage range SW pulse | SW | -3 | 10 | V | Pulse < 20 ns, E = 5 J | 4 | |
| High-side and low-side FET drain-source voltage DC | 6.5 | V | DC | 4 | |||
| High-side and low-side FET drain-source voltage AC | 7.5 | V | AC, Pulse < 50 ns | 4 | |||
| PGD voltage | PGD | -0.3 | 6.5 | V | 4 | ||
| COMP voltage | COMP | -0.3 | 6.5 | V | 4 | ||
| PGND voltage | PGND | -0.3 | 0.3 | V | 4 | ||
| Operation ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Storage temperature | TS | -55 | 150 | °C | 4 | ||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Electrostatic discharge, Human Body Model (HBM) | 2000 | V | 4 | ||||
| Electrostatic discharge, Charged Device Model (CDM) | 500 | V | 4 | ||||
| Lead temperature | 300 | °C | 1.6 mm (1/16 inch) from case for 10 seconds | 4 | |||
| Input voltage range VIN | VIN | 2.9 | 5.5 | V | 4 | ||
| VDD supply voltage | VDD | 2.9 | 5.5 | V | 4 | ||
| VBST voltage | VBST | -0.1 | 13.5 | V | 4 | ||
| VBST voltage with respect to SW | VBST (with respect to SW) | -0.1 | 6 | V | 4 | ||
| EN voltage | EN | -0.1 | 3.5 | V | 4 | ||
| FB and PS voltage | FB, PS | -0.1 | 3.5 | V | 4 | ||
| Output voltage range SW | SW | -1 | 6.5 | V | 4 | ||
| PGD voltage | PGD | -0.1 | 6 | V | 4 | ||
| COMP voltage | COMP | -0.1 | 3.5 | V | 4 | ||
| PGND voltage | PGND | -0.1 | 0.1 | V | 4 | ||
| Junction temperature range | TJ | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RJA | 45 | °C/W | 4 | |||
| VIN operation voltage | VIN | 2.9 | 5.5 | V | Nominal input voltage range | 5 | |
| VDD internal bias voltage | VDD | 2.9 | 5.5 | V | Nominal 3.3 V input voltage range | 5 | |
| Power good low voltage | 200 | 400 | mV | Pull-down voltage with 4 mA sink current | 5 | ||
| Power good high leakage current | -2 | 0 | 2 | A | 5 | ||
| Power good threshold, feedback lower voltage limit | 80 | 83 | 86 | %Vref | Feedback lower voltage limit | 5 | |
| Power good threshold, feedback higher voltage limit | 114 | 117 | 120 | %Vref | Feedback higher voltage limit | 5 | |
| Output over-voltage protection threshold at FB | 114 | 117 | 120 | %Vref | 5 | ||
| Over-voltage blanking time | tOVPDLY | 1 | 1.7 | 2.5 | s | Time from FB higher than 20% of Vref to OVP fault | 5 |
| Output under-voltage protection threshold at FB | 80 | 83 | 86 | %Vref | 5 | ||
| VDD quiescent current | IVDD | 2.2 | 3.5 | mA | EN = 'HI', no switching | 5 | |
| Reference voltage at FB | VREF | 594 | 600 | 606 | mV | −40°C < TA < 85°C | 5 |
| Over-current limit on high-side FET | 6.9 | 7.2 | 8.1 | A | When Iout exceeds this threshold for 4 consecutive cycles. Vin = 3.3 V, Vout = 1.5 V with 1 H inductor, TA = +25°C | 5 | |
| One-time over-current latch-off on low-side FET | 7 | 8.1 | A | Vin = 3.3 V, Vout = 1.5 V with 1 H inductor, TA = +25°C | 5 | ||
| Zero crossing comparator internal offset | -4.5 | -3 | -1.5 | mV | PGND−SWN, Automatic CCM/DCM mode | 5 | |
| EN high threshold voltage | 1.1 | 1.18 | 1.3 | V | 6 | ||
| EN hysteresis | 0.18 | 0.24 | V | 6 | |||
| PS pin source pull-up current | 8 | 10 | 12 | A | When enabled | 6 | |
| Switching frequency control | 0.99 | 1.1 | 1.21 | MHz | Forced CCM mode | 6 | |
| Minimum OFF time | 100 | 140 | ns | FCCM mode or Automatic CCM/DCM mode | 6 | ||
| Maximum duty cycle, FCCM or Automatic CCM/DCM mode | 84 | 89 | % | FsW = 1.1 MHz, 0°C < TA < 85°C | 6 | ||
| Thermal shutdown threshold | 130 | 140 | 150 | °C | 6 |
CAD (KiCad official)
- Symbol:
NCP3135MNTXG - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ncp3135mntxg-etched.step/ncp3135mntxg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp3135mntxg.step/ncp3135mntxg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (13 pp, sha256
2fcd1969c68829e5, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NCP3135MNTXG
**onsemi** · DC-DC Converters · QFN-16-EP(3x3)
NCP3135MNTXG from onsemi, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Logic control to enable the switcher, internally pulled up to VDD with a 1.35 M resistor. |
| 2 | NC | unconnected | Not connected. |
| 3 | PGD | output | Open-drain power good output, which the Power Good Monitor section describes as a 5 mA pull-down output. |
| 4 | VBST | power_out | Gate drive voltage for the high-side FET; connect a capacitor from this pin to SW. |
| 5 | SW | output | Switch node between the high-side MOSFET and the low-side MOSFET. |
| 6 | SW | output | Switch node between the high-side MOSFET and the low-side MOSFET. |
| 7 | SW | output | Switch node between the high-side MOSFET and the low-side MOSFET. |
| 8 | PS | input | Mode configuration pin with a 10 µA pull-up: pulled high or floating selects Forced Continuous Conduction Mode, and a resistor equal to or lower than 174 k to GND selects Automatic CCM/DCM. |
| 9 | COMP | output | Output of the error amplifier. |
| 10 | FB | input | Feedback pin; connect to a resistor divider to set the desired output voltage. |
| 11 | AGND | power_in | Analog ground, to be separated from power ground and joined to it at a single point per the layout guidelines. |
| 12 | VDD | power_in | Power supply input for the control circuitry. |
| 13 | VIN | power_in | Power input for power conversion and gate driver supply. |
| 14 | VIN | power_in | Power input for power conversion and gate driver supply. |
| 15 | PGND | power_in | Power ground. |
| 16 | PGND | power_in | Power ground. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | QFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN, VDD, PS, EN | -0.3 | | 6.5 | V | | 4 |
| VBST voltage | VBST | -0.3 | | 17 | V | | 4 |
| VBST voltage with respect to SW | VBST (with respect to SW) | -0.3 | | 6.5 | V | | 4 |
| FB voltage | FB | -0.3 | | 3.7 | V | | 4 |
| Output voltage range SW DC | SW | -1 | | 6.5 | V | DC | 4 |
| Output voltage range SW pulse | SW | -3 | | 10 | V | Pulse < 20 ns, E = 5 J | 4 |
| High-side and low-side FET drain-source voltage DC | | | | 6.5 | V | DC | 4 |
| High-side and low-side FET drain-source voltage AC | | | | 7.5 | V | AC, Pulse < 50 ns | 4 |
| PGD voltage | PGD | -0.3 | | 6.5 | V | | 4 |
| COMP voltage | COMP | -0.3 | | 6.5 | V | | 4 |
| PGND voltage | PGND | -0.3 | | 0.3 | V | | 4 |
| Operation ambient temperature | TA | -40 | | 125 | °C | | 4 |
| Storage temperature | TS | -55 | | 150 | °C | | 4 |
| Junction temperature | TJ | -40 | | 150 | °C | | 4 |
| Electrostatic discharge, Human Body Model (HBM) | | | | 2000 | V | | 4 |
| Electrostatic discharge, Charged Device Model (CDM) | | | | 500 | V | | 4 |
| Lead temperature | | | | 300 | °C | 1.6 mm (1/16 inch) from case for 10 seconds | 4 |
| Input voltage range VIN | VIN | 2.9 | | 5.5 | V | | 4 |
| VDD supply voltage | VDD | 2.9 | | 5.5 | V | | 4 |
| VBST voltage | VBST | -0.1 | | 13.5 | V | | 4 |
| VBST voltage with respect to SW | VBST (with respect to SW) | -0.1 | | 6 | V | | 4 |
| EN voltage | EN | -0.1 | | 3.5 | V | | 4 |
| FB and PS voltage | FB, PS | -0.1 | | 3.5 | V | | 4 |
| Output voltage range SW | SW | -1 | | 6.5 | V | | 4 |
| PGD voltage | PGD | -0.1 | | 6 | V | | 4 |
| COMP voltage | COMP | -0.1 | | 3.5 | V | | 4 |
| PGND voltage | PGND | -0.1 | | 0.1 | V | | 4 |
| Junction temperature range | TJ | -40 | | 125 | °C | | 4 |
| Junction-to-ambient thermal resistance | RJA | | 45 | | °C/W | | 4 |
| VIN operation voltage | VIN | 2.9 | | 5.5 | V | Nominal input voltage range | 5 |
| VDD internal bias voltage | VDD | 2.9 | | 5.5 | V | Nominal 3.3 V input voltage range | 5 |
| Power good low voltage | | | 200 | 400 | mV | Pull-down voltage with 4 mA sink current | 5 |
| Power good high leakage current | | -2 | 0 | 2 | A | | 5 |
| Power good threshold, feedback lower voltage limit | | 80 | 83 | 86 | %Vref | Feedback lower voltage limit | 5 |
| Power good threshold, feedback higher voltage limit | | 114 | 117 | 120 | %Vref | Feedback higher voltage limit | 5 |
| Output over-voltage protection threshold at FB | | 114 | 117 | 120 | %Vref | | 5 |
| Over-voltage blanking time | tOVPDLY | 1 | 1.7 | 2.5 | s | Time from FB higher than 20% of Vref to OVP fault | 5 |
| Output under-voltage protection threshold at FB | | 80 | 83 | 86 | %Vref | | 5 |
| VDD quiescent current | IVDD | | 2.2 | 3.5 | mA | EN = 'HI', no switching | 5 |
| Reference voltage at FB | VREF | 594 | 600 | 606 | mV | −40°C < TA < 85°C | 5 |
| Over-current limit on high-side FET | | 6.9 | 7.2 | 8.1 | A | When Iout exceeds this threshold for 4 consecutive cycles. Vin = 3.3 V, Vout = 1.5 V with 1 H inductor, TA = +25°C | 5 |
| One-time over-current latch-off on low-side FET | | | 7 | 8.1 | A | Vin = 3.3 V, Vout = 1.5 V with 1 H inductor, TA = +25°C | 5 |
| Zero crossing comparator internal offset | | -4.5 | -3 | -1.5 | mV | PGND−SWN, Automatic CCM/DCM mode | 5 |
| EN high threshold voltage | | 1.1 | 1.18 | 1.3 | V | | 6 |
| EN hysteresis | | | 0.18 | 0.24 | V | | 6 |
| PS pin source pull-up current | | 8 | 10 | 12 | A | When enabled | 6 |
| Switching frequency control | | 0.99 | 1.1 | 1.21 | MHz | Forced CCM mode | 6 |
| Minimum OFF time | | | 100 | 140 | ns | FCCM mode or Automatic CCM/DCM mode | 6 |
| Maximum duty cycle, FCCM or Automatic CCM/DCM mode | | | 84 | 89 | % | FsW = 1.1 MHz, 0°C < TA < 85°C | 6 |
| Thermal shutdown threshold | | 130 | 140 | 150 | °C | | 6 |
## CAD (KiCad official)
- Symbol: `NCP3135MNTXG`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `ncp3135mntxg-etched.step` / `ncp3135mntxg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp3135mntxg.step` / `ncp3135mntxg.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914060930781184) (13 pp, sha256 `2fcd1969c68829e5`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ncp3135mntxg-datasheet.pdf)