# NCP308MTADJTBG

**onsemi** · Monitors & Reset Circuits · DFN-6-EP(2x2)

NCP308MTADJTBG from onsemi, in a DFN-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply voltage (1.6 to 5.5 V); a 0.1 uF ceramic capacitor placed close to this pin is helpful for transient and parasitic suppression. |
| 2 | SENSE | input | Sense input for the monitored voltage; RESET is asserted if the voltage drops below threshold VIT (0.405 V min on adjustable version), and it can monitor any voltage lower than VDD. |
| 3 | CT | passive | Reset delay time setting pin: tied to VDD through 40 k to 200 k gives fixed 300 ms, open gives fixed 20 ms, and a capacitor to ground (>=100 pF) gives a programmable 1.25 ms to 10 s delay. |
| 4 | MR | input | Manual Reset input; MR low asserts RESET, and it is internally tied to VDD by a 90 k pull-up resistor so it may be left unconnected. |
| 5 | GND | power_in | Ground terminal, to be connected to PCB ground reference. |
| 6 | RESET | output | Active-low open-drain N-channel MOSFET reset output that needs a pull-up resistor of 10 k to 1 M and can be pulled up to 5.5 V. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | DFN-6-EP(2x2) |
| Category | Power Management ICs |
| Pins | 7 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage Range | VDD | 1.6 |  | 5.5 | V | -40°C < TJ < +125°C | 5 |
| Minimum VDD Guaranteed RESET Output Valid | VDD(min) |  | 0.5 | 0.8 | V |  | 5 |
| Supply Current | IDD |  | 1.6 | 5 | A | VDD = 3.3V, RESET not asserted, MR, RESET, CT open | 5 |
| Supply Current | IDD |  | 1.6 | 6 | A | VDD = 5.5V, RESET not asserted, MR, RESET, CT open | 5 |
| Low-level output voltage of RESET | VOL |  |  | 0.3 | V | 1.3V ≤ VDD < 1.6V, IOL = 0.4 mA | 5 |
| Low-level output voltage of RESET | VOL |  |  | 0.4 | V | 1.6V ≤ VDD ≤ 5.5V, IOL = 1.0 mA | 5 |
| Negative going SENSE threshold voltage accuracy | VIT% | -1.75 | 0.75 | 1.75 | % |  | 5 |
| Negative going SENSE threshold voltage accuracy | VIT% | -0.31 |  | 0.31 | % | TJ = +25°C | 5 |
| Negative going SENSE threshold voltage accuracy | VIT% | -1 | 0.5 | 1 | % | -20°C < TJ < +85°C | 5 |
| Hysteresis on VIT | VHYS | 1 |  | 3 | %VIT | 1.6V≤VDD≤4.2V | 5 |
| Hysteresis on VIT | VHYS | 1.75 |  | 3.75 | %VIT | 4.2V≤VDD≤5.5V | 5 |
| MR Internal pull-up resistance | RMR |  | 90 |  | kΩ |  | 5 |
| Input current at SENSE pin | ISENSE |  |  | 10 | nA | NCP308XXADJ VSENSE = VIT | 5 |
| RESET leakage Current | IOH |  |  | 300 | nA | VRESET = 5.5 V, RESET not asserted | 5 |
| Input capacitance, CT pin | CIN |  | 5 |  | pF | VIN = 0 V to VDD | 5 |
| Input capacitance, other pins | CIN |  | 5 |  | pF | VIN = 0 V to 5.5 V | 5 |
| MR logic low input | VIL | 0 |  | 0.3 | V | max is 0.3 VDD | 5 |
| MR logic high input | VIH | 0.7 |  |  | V | min is 0.7 VDD, max VDD | 5 |
| Input pulse width to assert RESET (SENSE) | tw |  | 20 |  | µs | VIH = 1.05 VIT, VIL = 0.95 VIT | 5 |
| Input pulse width to assert RESET (MR) | tw |  | 150 |  | ns | VIH = 0.7 VDD, VIL = 0.3 VDD | 5 |
| Propagation delay from MR | tP1 |  |  | 150 | ns | VIH = 0.7 VDD, VIL = 0.3 VDD | 5 |
| Propagation delay from SENSE | tP2 |  |  | 20 | µs | VIH = 1.05 VIT, VIL = 0.95 VIT | 5 |
| Input voltage range | VDD | -0.3 |  | 6 | V |  | 4 |
| CT, RESET, MR voltage range | VCT | -0.3 |  | 6 | V | -0.3 to VDD + 0.3 ≤ 6.0 | 4 |
| Current through CT pin | ICT |  |  | 10 | mA |  | 4 |
| SENSE pin voltage |  | -0.3 |  | 8 | V |  | 4 |
| RESET pin current |  |  |  | 5 | mA |  | 4 |
| Thermal Resistance Junction-to-Air WDFN6 | RθJA |  | 220 |  | °C/W | WDFN6 | 4 |
| ESD HBM | ESD HBM |  |  | 2000 | V |  | 4 |
| ESD MM | ESD MM |  |  | 100 | V |  | 4 |
| ESD CDM | ESD CDM |  |  | 500 | V |  | 4 |
| Latch up Current, all pins except digital | ILU | -100 |  | 100 | mA | All pins, except digital pins | 4 |
| Latch up Current, digital pins (MR) | ILU | -10 |  | 10 | mA | Digital pins (MR) | 4 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 4 |
| Maximum Junction Temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Reset delay time | tD |  | 20 |  | ms | CT = Open (Guaranteed by design and characterization) | 5 |
| Reset delay time | tD |  | 300 |  | ms | CT = VDD (Guaranteed by design and characterization) | 5 |
| Reset delay time | tD |  | 1.25 |  | ms | CT = 100 pF (Guaranteed by design and characterization) | 5 |
| Reset delay time | tD |  | 1200 |  | ms | CT = 180 nF (Guaranteed by design and characterization) | 5 |

## CAD (KiCad official)

- Symbol: `NCP308MTADJTBG`
- Footprint: `Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm`
- 3D model: DFN-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `ncp308mtadjtbg-etched.step` / `ncp308mtadjtbg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp308mtadjtbg.step` / `ncp308mtadjtbg.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncp308mtadjtb-d.pdf) (11 pp, sha256 `2bfa8a85cc0abcb1`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ncp308mtadjtbg-datasheet.pdf)