component
NCP3063DR2G
Public Made by Adomby adom
onsemi DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 17d ago |
| viewers | 17d ago |
| ncp3063dr2g-etched.glb | 17d ago |
| ncp3063dr2g-etched.step | 17d ago |
| ncp3063dr2g-hero.glb | 17d ago |
| ncp3063dr2g-hero.overlay.json | 17d ago |
| ncp3063dr2g.glb | 17d ago |
| ncp3063dr2g.kicad_mod | 17d ago |
| ncp3063dr2g.kicad_sym | 17d ago |
| ncp3063dr2g.lbr | 17d ago |
| ncp3063dr2g.step | 17d ago |
| package.json | 17d ago |
| page.json | 17d ago |
| README.md | 17d ago |
NCP3063DR2G
onsemi · DC-DC Converters · SOIC-8
NCP3063DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Switch Collector | output | Internal Darlington switch collector, rated 0 to +40 V, with switch current up to 1.5 A. |
| 2 | Switch Emitter | output | Internal Darlington switch emitter, rated −0.6 V to VCC when the transistor is off. |
| 3 | Timing Capacitor | input | Oscillator timing capacitor connection (CT) that sets the switching frequency; the pin voltage is limited to −0.2 V to +1.4 V. |
| 4 | GND | power_in | Ground pin for all internal circuits and the reference for the maximum ratings. |
| 5 | Comparator Inverting Input | input | Inverting input of the internal comparator, rated −0.2 V to VCC. |
| 6 | VCC | power_in | Voltage supply pin, rated 0 to +40 V. |
| 7 | Ipk Sense | input | Peak current sense input that monitors the voltage drop across an external resistor to limit peak current; rated −0.2 V to VCC + 0.2 V and the current limit sense voltage is 200 mV typical. |
| 8 | N.C. | unconnected | Pin not connected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Oscillator frequency | fOSC | 110 | 150 | 190 | kHz | VPin 5 = 0 V, CT = 2.2 nF, TJ = 25°C | 4 |
| Discharge to charge current ratio | IDISCHG / ICHG | 5.5 | 6 | 6.5 | − | Pin 7 to VCC, TJ = 25°C | 4 |
| Current limit sense voltage | VIPK(Sense) | 165 | 200 | 235 | mV | TJ = 25°C (Note 6) | 4 |
| Threshold voltage line regulation | REGLINE | -6 | 2 | 6 | mV | VCC = 5.0 V to 40 V | 4 |
| Comparator input bias current | ICII | -1000 | -100 | 1000 | nA | Vin = Vth | 4 |
| Threshold voltage tolerance (NCP3063 variant; NCP3063B/NCV3063 differ) | VTH | -1.5 | 1.5 | % | 4 | ||
| Operating junction temperature range (NCP3063) | TJ | 0 | 70 | °C | NCP3063 variant (Note 3) | 3 | |
| Supply voltage | VCC | 0 | 40 | V | Pin 6 | 3 | |
| Comparator inverting input voltage | VCII | -0.2 | V | Pin 5; upper limit printed as + VCC | 3 | ||
| Darlington switch collector voltage | VSWC | 0 | 40 | V | Pin 1 | 3 | |
| Darlington switch emitter voltage (transistor OFF) | VSWE | -0.6 | V | Pin 2, transistor OFF; upper limit printed as + VCC | 3 | ||
| Darlington switch collector to emitter voltage | VSWCE | 0 | 40 | V | Pin 1-2 | 3 | |
| Darlington switch current | ISW | 1.5 | A | 3 | |||
| Ipk sense voltage | VIPK | -0.2 | V | Pin 7; upper limit printed as VCC + 0.2 | 3 | ||
| Timing capacitor voltage | VTCAP | -0.2 | 1.4 | V | Pin 3 | 3 | |
| Storage temperature range | TSTG | -65 | 150 | °C | 3 | ||
| Maximum junction temperature | TJ MAX | 150 | °C | 3 | |||
| Thermal resistance, junction-to-air, SOIC-8 | RJA | 180 | °C/W | SOIC-8 package | 3 | ||
| Thermal resistance, junction-to-case, SOIC-8 | RJC | 45 | °C/W | SOIC-8 package | 3 |
CAD (KiCad official)
- Symbol:
NCP3063DR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp3063dr2g-etched.step/ncp3063dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp3063dr2g.step/ncp3063dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (19 pp, sha256
706fe13c74fc8342, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).