main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers ncp163afcs280t2g: viewers · Ray 2d ago
ncp163afcs280t2g-etched.glb Publish 0.1.0 · Ray 2d ago
ncp163afcs280t2g-etched.step ncp163afcs280t2g: factory component page (tier=mfr) · Ray 2d ago
ncp163afcs280t2g-hero.glb ncp163afcs280t2g: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
ncp163afcs280t2g-hero.overlay.json Publish 0.1.0 · Ray 2d ago
ncp163afcs280t2g.glb Publish 0.1.0 · Ray 2d ago
ncp163afcs280t2g.kicad_mod Publish 0.1.0 · Ray 2d ago
ncp163afcs280t2g.kicad_sym Publish 0.1.0 · Ray 2d ago
ncp163afcs280t2g.lbr Publish 0.1.0 · Ray 2d ago
ncp163afcs280t2g.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier mfr, 4 pins · Ray 2d ago

NCP163AFCS280T2G

onsemi · Linear Voltage Regulators (LDO) · WLCSP-4(0.6x0.6)

NCP163AFCS280T2G from onsemi, in a WLCSP-4(0.6x0.6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
A1 IN power_in Input voltage supply pin; the operating input voltage range is 2.2 V to 5.5 V, with an absolute maximum of -0.3 V to 6 V.
A2 OUT power_out Regulated output voltage that should be bypassed with a small 1 µF ceramic capacitor placed close to the pin.
B1 EN input Chip enable: VEN below 0.4 V disables the regulator and VEN above 1.2 V enables the LDO.
B2 GND power_in Common ground connection.

Key specifications

Parameter Value
Manufacturer onsemi
Package WLCSP-4(0.6x0.6)
Category Power Management ICs
Pins 4

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Input Voltage VIN 2.2 5.5 V 3
Operating Junction Temperature TJ -40 125 °C Electrical characteristics operating range 3
Output Voltage Accuracy VOUT -2 2 % VIN = (VOUT(NOM) + 1 V) to 5.5 V; 0 mA ≤ IOUT ≤ 250 mA 3
Dropout Voltage (WLCSP4 package) VDO 95 160 mV IOUT = 250 mA, VOUT(NOM) = 2.8 V, WLCSP/XDFN4 packages 3
Output Current Limit ICL 250 700 mA VOUT = 90% VOUT(NOM) 3
EN Input Voltage High VENH 1.2 V EN Input Voltage “H” 3
EN Input Voltage Low VENL 0.4 V EN Input Voltage “L” 3
Line Transient (VIN rising) TranLINE -1 mV VIN = (VOUT(NOM) + 1 V) to (VOUT(NOM) + 1.6 V) in 30 µs, IOUT = 1 mA 4
Line Transient (VIN falling) TranLINE 1 mV VIN = (VOUT(NOM) + 1.6 V) to (VOUT(NOM) + 1 V) in 30 µs, IOUT = 1 mA 4
Load Transient (load step up) TranLOAD -40 mV IOUT = 1 mA to 200 mA in 10 µs 4
Load Transient (load step down) TranLOAD 40 mV IOUT = 200 mA to 1 mA in 10 µs 4
Absolute Maximum Input Voltage VIN -0.3 6 V 2
Absolute Maximum Output Voltage VOUT -0.3 6 V VOUT ≤ VIN + 0.3, max. 6 V 2
Absolute Maximum Chip Enable Input Voltage VCE -0.3 6 V 2
Maximum Junction Temperature TJ 150 °C 2
Storage Temperature TSTG -55 150 °C 2
ESD Capability, Human Body Model ESDHBM 2000 V Per EIA/JESD22-A114 2
ESD Capability, Machine Model ESDMM 200 V Per EIA/JESD22-A115 2
ESD Capability, Charged Device Model ESDCDM 1000 V Per EIA/JESD22-C101 2
Thermal Resistance, Junction-to-Air (WLCSP4) RθJA 108 °C/W JEDEC board, Note 3 3
Line Regulation LineReg 0.02 %/V VOUT(NOM) + 1 V ≤ VIN ≤ 5.5 V 3
Load Regulation (WLCSP, XDFN4) LoadReg 0.001 %/mA IOUT = 1 mA to 250 mA 3
Short Circuit Current ISC 690 mA VOUT = 0 V 3
Quiescent Current IQ 12 20 µA IOUT = 0 mA 3
Shutdown Current IDIS 0.01 1 µA VEN ≤ 0.4 V, VIN = 4.8 V 3
EN Pull Down Current IEN 0.2 0.5 µA VEN = 4.8 V 3
Turn-On Time 120 µs COUT = 1 µF, from assertion of VEN to VOUT = 95% VOUT(NOM) 3
Power Supply Rejection Ratio at 100 Hz PSRR 91 dB IOUT = 20 mA, f = 100 Hz 3
Power Supply Rejection Ratio at 1 kHz PSRR 92 dB IOUT = 20 mA, f = 1 kHz 3
Power Supply Rejection Ratio at 10 kHz PSRR 85 dB IOUT = 20 mA, f = 10 kHz 3
Power Supply Rejection Ratio at 100 kHz PSRR 60 dB IOUT = 20 mA, f = 100 kHz 3
Output Voltage Noise (IOUT = 1 mA) VN 8 µVRMS f = 10 Hz to 100 kHz, IOUT = 1 mA 4
Output Voltage Noise (IOUT = 250 mA) VN 6.5 µVRMS f = 10 Hz to 100 kHz, IOUT = 250 mA 4
Thermal Shutdown Threshold (rising) TSDH 160 °C Temperature rising 4
Thermal Shutdown Threshold (falling) TSDL 140 °C Temperature falling 4
Active Output Discharge Resistance RDIS 280 Ω VEN < 0.4 V, Version A only 4

CAD (KiCad official)

  • Symbol: NCP163AFCS280T2G
  • Footprint: Package_CSP:WLCSP-4_0.64x0.64mm_Layout2x2_P0.35mm
  • 3D model: WLCSP-4(0.6x0.6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.35 mm nominal DSBGA height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ncp163afcs280t2g-etched.step / ncp163afcs280t2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp163afcs280t2g.step / ncp163afcs280t2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (23 pp, sha256 024c06f95e392f4d, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF