component
NCP1631DR2G
Public Made by Adomby adom
onsemi AC-DC Controllers And Regulators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownNCP1631DR2G
onsemi · AC-DC Controllers And Regulators · SOIC-16
NCP1631DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ZCD2 | input | Zero current detection input for phase 2 of the interleaved PFC stage; apply the auxiliary winding voltage to detect inductor core reset and the MOSFET drain-source valley. |
| 2 | FB | input | Receives a portion of the pre-converter output voltage for regulation and 'output low' detection (VOUTL), which speeds up the loop response when the output drops below 95.5% of the wished level. |
| 3 | Rt | passive | A resistor between this pin and ground adjusts the maximum on-time for both phases and hence the maximum power the PFC stage can deliver. |
| 4 | OSC | passive | Connect a capacitor to set the clamp frequency of the PFC stage; the circuit delays the next cycle until the core is reset, so the stage can operate in Critical Conduction Mode. |
| 5 | Vcontrol | output | Error amplifier output; the capacitor to ground sets the regulation loop bandwidth (typically below 20 Hz), and the pin is grounded when the circuit is off to give a soft-start. |
| 6 | FFOLD | passive | A resistor to ground adjusts the oscillator charge current, clamped not to exceed 100 µA and proportional to power level, for frequency fold-back at light load. |
| 7 | BO | input | Brown-out detection input fed with an averaged portion of the input voltage; a 50-ms internal delay blanks short mains interruptions, a 7-µA current source gives programmable hysteresis, and grounding the pin disables the part. |
| 8 | OVP / UVP | input | Output over/under-voltage sense; the circuit turns off when the pin goes below 480 mV (UVP) and disables the drive while the pin exceeds 2.5 V (OVP). |
| 9 | CS | input | Monitors a negative voltage proportional to the coil current, used to limit the maximum coil current and protect against in-rush currents. |
| 10 | Latch | input | Applying a voltage higher than 2.5 V latches off the circuit; reset by a brown-out detection or by forcing VCC below VCCRST (4 V typically). |
| 11 | DRV2 | output | Gate drive output for phase 2 of the interleaved PFC stage, a totem pole drive with +0.5/-0.8 A capability. |
| 12 | VCC | power_in | Positive supply of the IC; starts operating when VCC exceeds 12 V and turns off below 10 V (typical), with an operating range of 9.5 V to 20 V after start-up. |
| 13 | GND | power_in | Connect to the pre-converter ground. |
| 14 | DRV1 | output | Gate drive output for phase 1 of the interleaved PFC stage, a totem pole drive with +0.5/-0.8 A capability. |
| 15 | REF5V/pfcOK | output | High (5 V) when the PFC stage is in normal steady state and low otherwise, informing the downstream converter that the PFC stage is ready. |
| 16 | ZCD1 | input | Zero current detection input for phase 1 of the interleaved PFC stage; apply the auxiliary winding voltage to detect inductor core reset and the MOSFET drain-source valley. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum Power Supply Voltage | VCC(MAX) | -0.3 | 20 | V | Continuous | 2 | |
| Maximum Voltage on DRV Pins | DRVMAX | -0.3 | V | 2 | |||
| Maximum Input Voltage on Low Power Pins | VMAX | -0.3 | 9 | V | 2 | ||
| VControl Pin Maximum Input Voltage | VControl(MAX) | -0.3 | V | 2 | |||
| Maximum Power Dissipation | PD | 550 | mW | TA = 70°C | 2 | ||
| Operating Junction Temperature Range | TJ | -55 | 150 | °C | 2 | ||
| Storage Temperature Range | TS(MAX) | -65 | 150 | °C | 2 | ||
| Lead Temperature (Soldering) | TL(MAX) | 300 | °C | 10 s | 2 | ||
| Supply Voltage Startup Threshold | VCC(on) | 11 | 11.85 | 12.7 | V | VCC increasing | 3 |
| Minimum Operating Voltage | VCC(off) | 9.5 | 10 | 10.5 | V | VCC decreasing | 3 |
| Hysteresis VCC(on), VCC(off) | VCC(hyst) | 1.5 | 1.85 | V | 3 | ||
| Internal Logic Reset | VCC(reset) | 4 | 5.75 | 7.5 | V | VCC decreasing | 3 |
| Startup current | ICC(start) | 35 | 100 | µA | VCC = 9.4 V | 3 | |
| Supply Current | ICC1 | 5 | 7 | mA | Device Enabled/No output load on pin6; Fsw = 130 kHz (Note 4) | 3 | |
| Clamping Charging Current | IOSC(clamp) | 30 | 35 | 38.5 | µA | Pin 6 open; TJ = −55°C to +125°C (Note 6) | 3 |
| Charge Current with no frequency foldback | IOSC(CH1) | 120 | 140 | 154 | µA | Pin 6 grounded; TJ = −55°C to +125°C (Note 6) | 3 |
| Maximum Discharge Current with no frequency foldback | IOSC(DISCH1) | 90 | 105 | 115.5 | µA | Pin 6 grounded; TJ = −55°C to +125°C (Note 6) | 3 |
| Current Sense Protection Threshold | IILIM1 | 202 | 210 | 226 | µA | TJ = 25°C | 3 |
| Current Sense Protection Threshold | IILIM1 | 173 | 210 | 226 | µA | TJ = −55°C to +125°C (Note 6) | 3 |
| Threshold for In-rush Current Detection | Iin−rush | 10.4 | 14 | 17 | µA | TJ = −55°C to +125°C | 3 |
| Drive Resistance DRV1 Sink | RSNK1 | 7 | 15 | Ω | Ipin14 = 100 mA | 3 | |
| Drive Resistance DRV1 Source | RSRC1 | 15 | 25 | Ω | Ipin14 = −100 mA | 3 | |
| Drive Resistance DRV2 Sink | RSNK2 | 7 | 15 | Ω | Ipin11 = 100 mA | 3 | |
| Drive Resistance DRV2 Source | RSRC2 | 15 | 25 | Ω | Ipin11 = −100 mA | 3 | |
| Feedback Voltage Reference | VREF | 2.44 | 2.5 | 2.56 | V | 4 | |
| Pin 5 Source Current when (Vout(low) Detect) is activated | IControl(boost) | 178 | 230 | 276 | µA | TJ = −55°C to +125°C (Note 6) | 4 |
| Pin 5 Voltage | VControl(clamp) | 3 | 3.6 | 4.2 | V | @ Vpin2 = 2.4 V | 4 |
| Pin 5 Voltage | VControl(MIN) | 0 | 0.6 | 1.2 | V | @ Vpin2 = 2.6 V | 4 |
| Pin 5 Voltage range | VControl(range) | 2.7 | 3 | 3.3 | V | 4 | |
| Ratio (Vout(low) Detect Threshold / VREF) | Vout(low)/VREF | 95 | 95.5 | 96 | % | FB falling | 4 |
| Duty Cycle | DMIN | 0 | % | Vpin2 = 3 V | 4 | ||
| Maximum DRV1 and DRV2 On-Time | ton1 | 13 | 19.5 | 22.5 | µs | TJ = −55°C to +125°C; Vpin7 = 1.1 V, Ipin3 = 50 µA (Note 6) | 5 |
| Maximum DRV1 and DRV2 On-Time | ton2 | 1 | 1.35 | 1.6 | µs | TJ = −55°C to +125°C; Vpin7 = 1.1 V, Ipin3 = 200 µA (Note 5) | 5 |
| Maximum DRV1 and DRV2 On-Time | ton3 | 3.7 | 5 | 6 | µs | TJ = −55°C to +125°C; Vpin7 = 2.2 V, Ipin3 = 100 µA (Note 5) | 5 |
| Maximum DRV1 and DRV2 On-Time | ton4 | 0.32 | 0.41 | 0.48 | µs | TJ = −55°C to +125°C; Vpin7 = 2.2 V, Ipin3 = 400 µA (Note 5) | 5 |
| Pin 3 voltage | VRt1 | 1.071 | 1.096 | 1.121 | V | VBO = Vpin7 = 1.1 V, Ipin3 = 50 µA | 5 |
| Pin 3 voltage | VRt3 | 2.169 | 2.196 | 2.223 | V | VBO = Vpin7 = 2.2 V, Ipin3 = 50 µA | 5 |
| Pin 3 Current Capability | IRt(MAX) | 1 | mA | 5 | |||
| ZCD Threshold Voltage | VZCD(TH),H | 0.4 | 0.5 | 0.6 | V | VZCD increasing | 5 |
| ZCD Threshold Voltage | VZCD(TH),L | 0.2 | 0.25 | 0.3 | V | VZCD falling | 5 |
| ZCD Watchdog Delay | tZCD | 80 | 200 | 320 | µs | 5 | |
| Brown-Out Comparator Threshold | VBO(TH) | 0.97 | 1 | 1.03 | V | 5 | |
| Brown-Out Current Source | IBO | 5.7 | 7 | 8 | µA | TJ = −55°C to +125°C (Note 6) | 5 |
| Brown-Out Blanking Time | tBO(BLANK) | 38 | 50 | 63.5 | ms | TJ = −55°C to +125°C | 5 |
| Brown-Out Monitoring Window | tBO(window) | 38 | 50 | 62 | ms | 5 | |
| Current Capability of the BO Clamp | IBO(clamp) | 100 | µA | 5 | |||
| Hysteresis VBO(TH), VBO(clamp) | VBO(HYS) | 10 | 35 | 60 | mV | Ipin7 = −100 µA | 5 |
| Over-Voltage Protection Threshold | VOVP | 2.425 | 2.5 | 2.575 | V | 5 | |
| Ratio (VOVP / VREF) | VOVP/VREF | 99.2 | 99.7 | 100.2 | % | 5 | |
| Ratio UVP Threshold over VREF | VUVP/VREF | 8 | 12 | 16 | % | 5 | |
| Pin 15 Voltage Low State | VREF5V(low) | 60 | 120 | mV | Vpin7 = 0 V, Ipin15 = 250 µA | 6 | |
| Pin 15 Voltage High State | VREF5V(high) | 4.7 | 4.85 | 5.3 | V | Vpin7 = 0 V, Ipin15 = 5 mA | 6 |
| Current Capability | IREF5V | 5 | 10 | mA | 6 | ||
| Pin Latch Threshold for Shutdown | VLatch | 2.375 | 2.5 | 2.625 | V | 6 | |
| Thermal Shutdown Threshold | TSHDN | 130 | 140 | 150 | °C | 6 | |
| ESD Capability, HBM model | ESD HBM | 3 | kV | Human Body Model (Note 2) | 2 | ||
| ESD Capability, Machine Model | ESD MM | 250 | V | Machine Model (Note 2) | 2 | ||
| Thermal Resistance Junction-to-Air | RJ−A | 145 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
NCP1631DR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
ncp1631dr2g-etched.step/ncp1631dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp1631dr2g.step/ncp1631dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (25 pp, sha256
8db8af2fb647e499, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).