component
NCP1623ADR2G
Public Made by Adomby adom
onsemi AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
NCP1623ADR2G
onsemi · AC-DC Controllers And Regulators · SOIC-8
NCP1623ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback pin connected to the error amplifier input to monitor the PFC output voltage, detects output transients for DRE, SOVP and FOVP, has a built-in 250 nA sink current to trigger UVP if open, and on the NCP1623A sources IFB(LL) (25 µA typ) for lower low-line regulation. |
| 2 | VCC | power_in | IC operating current supply pin, with an absolute maximum of 30 V and a recommended operating range of 9.5 V to 30 V. |
| 3 | DRV | output | Totem pole gate drive output (-0.5 A / +0.8 A) for driving power FETs, internally clamped to 14 V max. |
| 4 | GND | power_in | Power supply ground. |
| 5 | DIS | input | A high level or open circuit disables the controller and reduces ICC bias current for low standby power (absolute maximum -0.3 to 9 V). |
| 6 | CS/ZCD | input | Multi-functional pin that monitors inductor current, the ZCD signal and input/output voltage, with an external impedance that should be higher than 7 kΩ. |
| 7 | NC | unconnected | True no connect; printed circuit board traces are allowable. |
| 8 | VCTRL | output | Error amplifier output where the feedback compensation network to ground sets the loop bandwidth, and it is grounded at IC reset to provide soft-start at the next startup. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Input | VCC | -0.3 | 30 | V | 5 | ||
| CS/ZCD Pin voltage | CS/ZCD | -0.3 | 11.5 | V | with 5 mA of clamp current | 5 | |
| Feedback Pin | FB | -0.3 | 9 | V | 5 | ||
| VCTRL Pin | VCTRL | -0.3 | 9 | V | 5 | ||
| Disable Pin, SOIC-8 | DIS | -0.3 | 9 | V | 5 | ||
| Maximum Junction Temperature | TJ(MAX) | 150 | °C | 5 | |||
| Storage Temperature Range | TSTG | -60 | 150 | °C | 5 | ||
| Lead Temperature Soldering | TSLD | 260 | °C | Reflow (SMD styles only), Pb-free versions | 5 | ||
| ESD Capability, HBM | ESDHBM | 2 | kV | 5 | |||
| ESD Capability, CDM | ESDCDM | 1 | kV | 5 | |||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 5 | ||
| Thermal Resistance, Junction-to-Air, SOIC-8 | RJA | 153 | °C/W | JEDEC 51-3 (1s0p) board, 100 mm2 copper, 1 oz | 5 | ||
| VCC Turn-On Voltage | VCC(ON) | 9.75 | 10.5 | 11.25 | V | VCC rising | 6 |
| VCC Turn-Off Voltage | VCC(OFF) | 8.5 | 9 | 9.5 | V | VCC falling | 6 |
| VCC Turn-On/Off Hysteresis | VCC(HYS) | 1 | 1.5 | 2 | V | VCC(ON) - VCC(OFF) | 6 |
| VCC Reset Voltage | VCC(RST) | 6 | 7 | 8 | V | VCC falling | 6 |
| IC Start-Up Current | ICC(START) | 20 | 50 | µA | VCC = 7 V | 6 | |
| IC Operating Current without Switching | ICC1 | 0.5 | 1 | mA | No switching | 6 | |
| IC Operating Current when Switching | ICC2 | 2 | 3 | mA | fSW = 50 kHz, No CL load | 6 | |
| IC Sleep Mode Current, SOIC-8 | ICC(DIS) | 100 | µA | DIS pin high | 6 | ||
| DRV Rising Time | tR | 15 | 30 | 90 | ns | CL = 1 nF | 6 |
| DRV Falling Time | tF | 10 | 20 | 50 | ns | CL = 1 nF | 6 |
| DRV Source Resistance | ROH | 10 | 20 | Ω | 6 | ||
| DRV Sink Resistance | ROL | 7 | 15 | Ω | 6 | ||
| DRV High Clamp Voltage | VDRV(HIGH) | 10 | 12 | 14 | V | VCC = 30 V, RL = 33 k | 6 |
| Maximum On-Time at Low Line, Ver. A | tON(MAX-LL) | 10.8 | 12.5 | 14.2 | µs | 6 | |
| Maximum On-Time at High Line, Ver. A | tON(MAX-HL) | 4.2 | 5 | 5.8 | µs | 6 | |
| On-Time Ratio of Low and High Line | KTON(LL-HL) | 2 | 2.5 | 3 | tON(LL)/tON(HL) | 6 | |
| Minimum On Time at Low-Line | tON(MIN-LL) | 100 | 180 | 250 | ns | 6 | |
| Minimum On Time at High-Line | tON(MIN-HL) | 50 | 100 | 150 | ns | 6 | |
| Dead-Time 1 | tDT1 | 13 | 18 | 23 | µs | VCTRL = 0.63 V | 6 |
| Dead-Time 2 | tDT2 | 5.5 | 8.5 | 11.5 | µs | VCTRL = 0.75 V | 6 |
| VCTRL Frequency Foldback Enter Voltage | VCTRL(FF-EN) | 1.87 | 2.08 | 2.29 | V | VCTRL falling | 6 |
| VCTRL Frequency Foldback Exit Voltage | VCTRL(FF-EX) | 1.96 | 2.18 | 2.4 | V | VCTRL rising | 6 |
| VCTRL Frequency Foldback Hysteresis | VCTRL(FF-HYS) | 75 | 100 | 120 | mV | 6 | |
| Minimum Frequency | fMIN | 24 | 28 | 32 | kHz | 6 | |
| VCTRL Skip Enter Voltage | VCTRL(SKIP-EN) | 0.5 | 0.56 | 0.62 | V | VCTRL falling | 6 |
| VCTRL Skip Exit Voltage | VCTRL(SKIP-EX) | 0.55 | 0.62 | 0.68 | V | VCTRL rising | 6 |
| VCTRL Skip Hysteresis | VCTRL(SKIP-HYS) | 40 | 70 | 100 | mV | 6 | |
| FB Regulation Reference Voltage | VREF | 2.44 | 2.5 | 2.56 | V | 6 | |
| FB Source Current at Low Line, Ver. A | IFB(LL) | 23.75 | 25 | 26.25 | µA | 6 | |
| Error Amplifier Source Current | IEA(SOURCE) | 15 | 20 | 25 | µA | VFB = 2.4 V | 6 |
| Error Amplifier Sink Current | IEA(SINK) | -25 | -20 | -15 | µA | VFB = 2.6 V | 6 |
| Error Amplifier Gain | GEA | 110 | 200 | 290 | µS | 6 | |
| VCTRL Maximum Clamping Voltage | VCTRL(MAX) | 4 | 4.5 | 5 | V | VFB = 2 V | 6 |
| VCTRL Minimum Clamping Voltage | VCTRL(MIN) | 0.3 | 0.5 | 0.8 | V | VFB = 3 V | 6 |
| VCTRL Startup Source Current | IVCTRL(START) | 90 | 120 | 150 | µA | 6 | |
| FB DRE Enter Voltage Ratio | KFB(DRE-EN) | 94.5 | 95.5 | 96.5 | % | VFB(DRE-EN) / VREF | 7 |
| FB DRE Exit Voltage Ratio | KFB(DRE-EX) | 96.5 | 97.5 | 98.5 | % | VFB(DRE-EX) / VREF | 7 |
| FB DRE Hysteresis Ratio | KFB(DRE-HYS) | 1 | 2 | 3 | % | 7 | |
| VCTRL DRE Source Current | IVCTRL(DRE) | 180 | 215 | 250 | µA | 7 | |
| FB SOVP Enter Voltage Ratio | KFB(SOVP-EN) | 103.5 | 105 | 106.5 | % | VFB(SOVP-EN) / VREF | 7 |
| FB SOVP Exit Voltage Ratio | KFB(SOVP-EX) | 101.5 | 103 | 104.5 | % | VFB(SOVP-EX) / VREF | 7 |
| FB SOVP Hysteresis Ratio | KFB(SOVP-HYS) | 1 | 2 | 3 | % | 7 | |
| FB SOVP Enter Voltage Ratio at Low Line, Ver. A | KFB(SOVP-EN-LL) | 108.5 | 110 | 111.5 | % | VFB(SOVP-EN-LL) / VREF | 7 |
| FB SOVP Exit Voltage Ratio at Low Line, Ver. A | KFB(SOVP-EX-LL) | 106.5 | 108 | 109.5 | % | VFB(SOVP-EX-LL) / VREF | 7 |
| FB FOVP Enter Voltage Ratio | KFB(FOVP-EN) | 105.5 | 107 | 108.5 | % | VFB(FOVP-EN) / VREF | 7 |
| FB FOVP Exit Voltage Ratio | KFB(FOVP-EX) | 103.5 | 105 | 106.5 | % | VFB(FOVP-EX) / VREF | 7 |
| FB FOVP Enter Voltage Ratio at Low Line, Ver. A | KFB(FOVP-EN-LL) | 112.5 | 114 | 115.5 | % | VFB(FOVP-EN-LL) / VREF | 7 |
| FB UVP Enter Voltage | VFB(UVP-EN) | 240 | 300 | 360 | mV | VFB falling | 7 |
| FB UVP Exit Voltage | VFB(UVP-EX) | 470 | 530 | 590 | mV | VFB rising | 7 |
| CS Over-Current Protection Voltage | VCS(OCP) | 450 | 500 | 550 | mV | 7 | |
| CS Over-Stress Protection Voltage | VCS(OVS) | 675 | 750 | 825 | mV | 7 | |
| CS/ZCD Clamp Voltage | VCS/ZCD(CL) | 8 | 9.5 | 11.5 | V | ICS/ZCD = 5 mA | 7 |
| Thermal Shutdown Threshold | TLIMT | 150 | °C | Based on design and/or characterization | 8 |
CAD (KiCad official)
- Symbol:
NCP1623ADR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp1623adr2g-etched.step/ncp1623adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp1623adr2g.step/ncp1623adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (20 pp, sha256
ab805ac6e3abe359, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NCP1623ADR2G
**onsemi** · AC-DC Controllers And Regulators · SOIC-8
NCP1623ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback pin connected to the error amplifier input to monitor the PFC output voltage, detects output transients for DRE, SOVP and FOVP, has a built-in 250 nA sink current to trigger UVP if open, and on the NCP1623A sources IFB(LL) (25 µA typ) for lower low-line regulation. |
| 2 | VCC | power_in | IC operating current supply pin, with an absolute maximum of 30 V and a recommended operating range of 9.5 V to 30 V. |
| 3 | DRV | output | Totem pole gate drive output (-0.5 A / +0.8 A) for driving power FETs, internally clamped to 14 V max. |
| 4 | GND | power_in | Power supply ground. |
| 5 | DIS | input | A high level or open circuit disables the controller and reduces ICC bias current for low standby power (absolute maximum -0.3 to 9 V). |
| 6 | CS/ZCD | input | Multi-functional pin that monitors inductor current, the ZCD signal and input/output voltage, with an external impedance that should be higher than 7 kΩ. |
| 7 | NC | unconnected | True no connect; printed circuit board traces are allowable. |
| 8 | VCTRL | output | Error amplifier output where the feedback compensation network to ground sets the loop bandwidth, and it is grounded at IC reset to provide soft-start at the next startup. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Input | VCC | -0.3 | | 30 | V | | 5 |
| CS/ZCD Pin voltage | CS/ZCD | -0.3 | | 11.5 | V | with 5 mA of clamp current | 5 |
| Feedback Pin | FB | -0.3 | | 9 | V | | 5 |
| VCTRL Pin | VCTRL | -0.3 | | 9 | V | | 5 |
| Disable Pin, SOIC-8 | DIS | -0.3 | | 9 | V | | 5 |
| Maximum Junction Temperature | TJ(MAX) | | | 150 | °C | | 5 |
| Storage Temperature Range | TSTG | -60 | | 150 | °C | | 5 |
| Lead Temperature Soldering | TSLD | | | 260 | °C | Reflow (SMD styles only), Pb-free versions | 5 |
| ESD Capability, HBM | ESDHBM | | | 2 | kV | | 5 |
| ESD Capability, CDM | ESDCDM | | | 1 | kV | | 5 |
| Operating Junction Temperature Range | TJ | -40 | | 125 | °C | | 5 |
| Thermal Resistance, Junction-to-Air, SOIC-8 | RJA | | 153 | | °C/W | JEDEC 51-3 (1s0p) board, 100 mm2 copper, 1 oz | 5 |
| VCC Turn-On Voltage | VCC(ON) | 9.75 | 10.5 | 11.25 | V | VCC rising | 6 |
| VCC Turn-Off Voltage | VCC(OFF) | 8.5 | 9 | 9.5 | V | VCC falling | 6 |
| VCC Turn-On/Off Hysteresis | VCC(HYS) | 1 | 1.5 | 2 | V | VCC(ON) - VCC(OFF) | 6 |
| VCC Reset Voltage | VCC(RST) | 6 | 7 | 8 | V | VCC falling | 6 |
| IC Start-Up Current | ICC(START) | | 20 | 50 | µA | VCC = 7 V | 6 |
| IC Operating Current without Switching | ICC1 | | 0.5 | 1 | mA | No switching | 6 |
| IC Operating Current when Switching | ICC2 | | 2 | 3 | mA | fSW = 50 kHz, No CL load | 6 |
| IC Sleep Mode Current, SOIC-8 | ICC(DIS) | | | 100 | µA | DIS pin high | 6 |
| DRV Rising Time | tR | 15 | 30 | 90 | ns | CL = 1 nF | 6 |
| DRV Falling Time | tF | 10 | 20 | 50 | ns | CL = 1 nF | 6 |
| DRV Source Resistance | ROH | | 10 | 20 | Ω | | 6 |
| DRV Sink Resistance | ROL | | 7 | 15 | Ω | | 6 |
| DRV High Clamp Voltage | VDRV(HIGH) | 10 | 12 | 14 | V | VCC = 30 V, RL = 33 k | 6 |
| Maximum On-Time at Low Line, Ver. A | tON(MAX-LL) | 10.8 | 12.5 | 14.2 | µs | | 6 |
| Maximum On-Time at High Line, Ver. A | tON(MAX-HL) | 4.2 | 5 | 5.8 | µs | | 6 |
| On-Time Ratio of Low and High Line | KTON(LL-HL) | 2 | 2.5 | 3 | | tON(LL)/tON(HL) | 6 |
| Minimum On Time at Low-Line | tON(MIN-LL) | 100 | 180 | 250 | ns | | 6 |
| Minimum On Time at High-Line | tON(MIN-HL) | 50 | 100 | 150 | ns | | 6 |
| Dead-Time 1 | tDT1 | 13 | 18 | 23 | µs | VCTRL = 0.63 V | 6 |
| Dead-Time 2 | tDT2 | 5.5 | 8.5 | 11.5 | µs | VCTRL = 0.75 V | 6 |
| VCTRL Frequency Foldback Enter Voltage | VCTRL(FF-EN) | 1.87 | 2.08 | 2.29 | V | VCTRL falling | 6 |
| VCTRL Frequency Foldback Exit Voltage | VCTRL(FF-EX) | 1.96 | 2.18 | 2.4 | V | VCTRL rising | 6 |
| VCTRL Frequency Foldback Hysteresis | VCTRL(FF-HYS) | 75 | 100 | 120 | mV | | 6 |
| Minimum Frequency | fMIN | 24 | 28 | 32 | kHz | | 6 |
| VCTRL Skip Enter Voltage | VCTRL(SKIP-EN) | 0.5 | 0.56 | 0.62 | V | VCTRL falling | 6 |
| VCTRL Skip Exit Voltage | VCTRL(SKIP-EX) | 0.55 | 0.62 | 0.68 | V | VCTRL rising | 6 |
| VCTRL Skip Hysteresis | VCTRL(SKIP-HYS) | 40 | 70 | 100 | mV | | 6 |
| FB Regulation Reference Voltage | VREF | 2.44 | 2.5 | 2.56 | V | | 6 |
| FB Source Current at Low Line, Ver. A | IFB(LL) | 23.75 | 25 | 26.25 | µA | | 6 |
| Error Amplifier Source Current | IEA(SOURCE) | 15 | 20 | 25 | µA | VFB = 2.4 V | 6 |
| Error Amplifier Sink Current | IEA(SINK) | -25 | -20 | -15 | µA | VFB = 2.6 V | 6 |
| Error Amplifier Gain | GEA | 110 | 200 | 290 | µS | | 6 |
| VCTRL Maximum Clamping Voltage | VCTRL(MAX) | 4 | 4.5 | 5 | V | VFB = 2 V | 6 |
| VCTRL Minimum Clamping Voltage | VCTRL(MIN) | 0.3 | 0.5 | 0.8 | V | VFB = 3 V | 6 |
| VCTRL Startup Source Current | IVCTRL(START) | 90 | 120 | 150 | µA | | 6 |
| FB DRE Enter Voltage Ratio | KFB(DRE-EN) | 94.5 | 95.5 | 96.5 | % | VFB(DRE-EN) / VREF | 7 |
| FB DRE Exit Voltage Ratio | KFB(DRE-EX) | 96.5 | 97.5 | 98.5 | % | VFB(DRE-EX) / VREF | 7 |
| FB DRE Hysteresis Ratio | KFB(DRE-HYS) | 1 | 2 | 3 | % | | 7 |
| VCTRL DRE Source Current | IVCTRL(DRE) | 180 | 215 | 250 | µA | | 7 |
| FB SOVP Enter Voltage Ratio | KFB(SOVP-EN) | 103.5 | 105 | 106.5 | % | VFB(SOVP-EN) / VREF | 7 |
| FB SOVP Exit Voltage Ratio | KFB(SOVP-EX) | 101.5 | 103 | 104.5 | % | VFB(SOVP-EX) / VREF | 7 |
| FB SOVP Hysteresis Ratio | KFB(SOVP-HYS) | 1 | 2 | 3 | % | | 7 |
| FB SOVP Enter Voltage Ratio at Low Line, Ver. A | KFB(SOVP-EN-LL) | 108.5 | 110 | 111.5 | % | VFB(SOVP-EN-LL) / VREF | 7 |
| FB SOVP Exit Voltage Ratio at Low Line, Ver. A | KFB(SOVP-EX-LL) | 106.5 | 108 | 109.5 | % | VFB(SOVP-EX-LL) / VREF | 7 |
| FB FOVP Enter Voltage Ratio | KFB(FOVP-EN) | 105.5 | 107 | 108.5 | % | VFB(FOVP-EN) / VREF | 7 |
| FB FOVP Exit Voltage Ratio | KFB(FOVP-EX) | 103.5 | 105 | 106.5 | % | VFB(FOVP-EX) / VREF | 7 |
| FB FOVP Enter Voltage Ratio at Low Line, Ver. A | KFB(FOVP-EN-LL) | 112.5 | 114 | 115.5 | % | VFB(FOVP-EN-LL) / VREF | 7 |
| FB UVP Enter Voltage | VFB(UVP-EN) | 240 | 300 | 360 | mV | VFB falling | 7 |
| FB UVP Exit Voltage | VFB(UVP-EX) | 470 | 530 | 590 | mV | VFB rising | 7 |
| CS Over-Current Protection Voltage | VCS(OCP) | 450 | 500 | 550 | mV | | 7 |
| CS Over-Stress Protection Voltage | VCS(OVS) | 675 | 750 | 825 | mV | | 7 |
| CS/ZCD Clamp Voltage | VCS/ZCD(CL) | 8 | 9.5 | 11.5 | V | ICS/ZCD = 5 mA | 7 |
| Thermal Shutdown Threshold | TLIMT | 150 | | | °C | Based on design and/or characterization | 8 |
## CAD (KiCad official)
- Symbol: `NCP1623ADR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ncp1623adr2g-etched.step` / `ncp1623adr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp1623adr2g.step` / `ncp1623adr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncp1623a-d.pdf) (20 pp, sha256 `ab805ac6e3abe359`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ncp1623adr2g-datasheet.pdf)