component
NCP1611ADR2G
Public Made by Adomby adom
onsemi AC-DC Controllers & Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCP1611ADR2G
onsemi · AC-DC Controllers & Regulators · SOIC-8
NCP1611ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCONTROL | output | Error amplifier output; the network to ground sets the regulation loop bandwidth (typically below 20 Hz) and the pin is grounded when the circuit is off to provide soft-start. |
| 2 | VSENSE | input | Senses a portion of the instantaneous input voltage for brown-out detection (stops pulsing if below 0.9 V for more than 50 ms, resumes above 1.0 V) and line range detection (high-line above 2.2 V, low-line if below 1.7 V for more than 25 ms); grounding it disables the part. |
| 3 | FFCONTROL | output | Sources a current representative of the line current; a resistor to ground sets a voltage compared to the 2.5 V VREF for CrM versus dead-time generation, and cycles are skipped when the pin is below 0.65 V. |
| 4 | CS/ZCD | input | Monitors the MOSFET current for maximum current limitation and serves as the zero current detection input from the auxiliary winding (0.75 V ZCD threshold), requiring pin impedance of 3.9 kOhm or more. |
| 5 | GND | power_in | Connect this pin to the PFC stage ground. |
| 6 | DRV | output | Totem pole gate drive output with -0.5 A/+0.8 A capability for driving high gate charge power MOSFETs. |
| 7 | VCC | power_in | Positive supply of the IC; starts at 10.5 V (A version), turns off below 9.0 V typical, and operates from 9.5 V up to 35 V after start-up. |
| 8 | Feedback | input | Receives a portion of the PFC output voltage for regulation, Dynamic Response Enhancer (below 95.5% of target) and OVP/UVP comparators (soft OVP above 105% VREF, fast OVP at 107%, UVP below 12% VREF); a 250 nA sink current disables the part if the pin is open. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Start-Up Threshold, VCC increasing (A version) | VCC(on) | 9.75 | 10.5 | 11.25 | V | VCC increasing, A version | 4 |
| Minimum Operating Voltage, VCC falling | VCC(off) | 8.5 | 9 | 9.5 | V | VCC falling | 4 |
| Hysteresis (VCC(on) − VCC(off)), A version | VCC(HYST) | 0.75 | 1.5 | V | A version | 4 | |
| Start-Up Current | ICC(start) | 20 | 50 | µA | VCC = 9.4 V | 4 | |
| Operating Consumption, no switching | ICC(op)1 | 0.5 | 1 | mA | Vsense pin being grounded | 4 | |
| Operating Consumption, 50 kHz switching | ICC(op)2 | 2 | 3 | mA | 50 kHz switching, no load on DRV pin | 4 | |
| Dead-Time, VFFcontrol = 2.60 V | TDT1 | 0 | µs | VFFcontrol = 2.60 V (Note 6) | 4 | ||
| Dead-Time, VFFcontrol = 1.75 V | TDT2 | 14 | 18 | 22 | µs | VFFcontrol = 1.75 V | 4 |
| Dead-Time, VFFcontrol = 1.00 V | TDT3 | 32 | 38 | 44 | µs | VFFcontrol = 1.00 V | 4 |
| FFcontrol pin current | IDT1 | 180 | 200 | 220 | µA | Vsense = 1.4 V and Vcontrol maximum | 4 |
| FFcontrol pin current | IDT2 | 110 | 135 | 160 | µA | Vsense = 2.8 V and Vcontrol maximum | 4 |
| FFcontrol pin Skip Level, rising | VSKIP-H | 0.75 | 0.85 | V | VFFcontrol rising | 4 | |
| FFcontrol pin Skip Level, falling | VSKIP-L | 0.55 | 0.65 | V | VFFcontrol falling | 4 | |
| FFcontrol pin Skip Hysteresis | VSKIP-HYST | 50 | mV | 4 | |||
| DRV pin level at VCC close to VCC(off) | VDRVlow | 8 | V | with a 10 k resistor to GND | 4 | ||
| DRV pin level at VCC = 35 V | VDRVhigh | 10 | 12 | 14 | V | RL = 33 k, CL = 1 nF | 4 |
| Feedback Voltage Reference, 0°C to 125°C | VREF | 2.44 | 2.5 | 2.54 | V | from 0°C to 125°C | 4 |
| Feedback Voltage Reference, over temperature range | VREF | 2.42 | 2.5 | 2.54 | V | Over the temperature range | 4 |
| Error Amplifier Gain | GEA | 110 | 220 | 290 | µS | 4 | |
| VOUT Low Detect Threshold / VREF | VOUTL / VREF | 95 | 95.5 | 96 | % | guaranteed by design | 4 |
| VOUT Low Detect Hysteresis / VREF | HOUTL / VREF | 0.5 | % | guaranteed by design | 4 | ||
| Vcontrol Pin Source Current when VOUT Low Detect is activated | IBOOST | 180 | 220 | 250 | µA | 4 | |
| Current Sense Voltage Reference | VCS(th) | 450 | 500 | 550 | mV | 4 | |
| OCP Leading Edge Blanking Time | TLEB,OCP | 100 | 200 | 350 | ns | guaranteed by design | 5 |
| Overstress Leading Edge Blanking Time | TLEB,OVS | 50 | 100 | 170 | ns | guaranteed by design | 5 |
| OCP Delay from VCS/ZCD > VCS(th) to DRV low | TOCP | 40 | 200 | ns | dVCS/ZCD/dt = 10 V/µs | 5 | |
| Zero Current Detection, rising | VZCD(th)H | 675 | 750 | 825 | mV | VCS/ZCD rising | 5 |
| Zero Current Detection, falling | VZCD(th)L | 200 | 250 | 300 | mV | VCS/ZCD falling | 5 |
| ZCD comparator Hysteresis | VZCD(hyst) | 375 | 500 | mV | 5 | ||
| VZCD(th)H over VCS(th) Ratio | RZCD/CS | 1.4 | 1.5 | 1.6 | 5 | ||
| CS/ZCD Pin Bias Current | IZCD(bias) | 0.5 | 2 | µA | VCS/ZCD = 0.75 V | 5 | |
| (VCS/ZCD < VZCD(th)L) to (DRV high) | TZCD | 60 | 200 | ns | 5 | ||
| Minimum ZCD Pulse Width | TSYNC | 110 | 200 | ns | 5 | ||
| Watch Dog Timer | TWDG | 80 | 200 | 320 | µs | 5 | |
| Watch Dog Timer in OverStress Situation | TWDG(OS) | 400 | 800 | 1200 | µs | 5 | |
| Time-Out Timer | TTMO | 20 | 30 | 50 | µs | 5 | |
| Duty Cycle (static OVP) | DMIN | 0 | % | VFB = 3 V, Vcontrol Pin Open | 5 | ||
| Maximum On Time | TON(LL) | 22 | 25 | 29 | µs | Vsense = 1.4 V and Vcontrol maximum (CrM) | 5 |
| On Time | TON(LL)2 | 10.5 | 12.5 | 14 | µs | Vsense = 1.4 V and Vcontrol = 2.5 V (CrM) | 5 |
| Maximum On Time | TON(HL) | 7.3 | 8.5 | 9.6 | µs | Vsense = 2.8 V and Vcontrol maximum (CrM) | 5 |
| Minimum On Time | TON(LL)(MIN) | 200 | ns | Vsense = 1.4 V (not tested, guaranteed by characterization) | 5 | ||
| Minimum On Time | TON(HL)(MIN) | 100 | ns | Vsense = 2.8 V (not tested, guaranteed by characterization) | 5 | ||
| Soft OVP Threshold / VREF | RsoftOVP | 104 | 105 | 106 | % | VFB rising, guaranteed by design | 5 |
| Soft OVP Hysteresis / VREF | RsoftOVP(HYST) | 1.5 | 2 | 2.5 | % | guaranteed by design | 5 |
| Fast OVP Threshold / VREF | RfastOVP2 | 106 | 107 | 108 | % | VFB rising, guaranteed by design | 5 |
| UVP Threshold / VREF | RUVP | 8 | 12 | 16 | % | VFB rising, guaranteed by design | 5 |
| UVP Hysteresis / VREF | RUVP(HYST) | 1 | % | guaranteed by design | 5 | ||
| FB Pin Bias Current | (IB)FB | 50 | 200 | 450 | nA | VFB = VOVP and VFB = VUVP | 5 |
| Brown-Out Threshold, Vsense rising | VBOH | 0.96 | 1 | 1.04 | V | Vsense rising | 5 |
| Brown-Out Threshold, Vsense falling | VBOL | 0.86 | 0.9 | 0.94 | V | Vsense falling | 5 |
| Brown-Out Comparator Hysteresis | VBO(HYST) | 60 | 100 | mV | 5 | ||
| Brown-Out Blanking Time | TBO(blank) | 35 | 50 | 65 | ms | 5 | |
| Vcontrol Pin Sink Current | ICONTROL(BO) | 40 | 50 | 60 | µA | Vsense < VBOL | 5 |
| Line Range Detection Threshold, rising | VHL | 2.1 | 2.2 | 2.3 | V | Vsense rising | 6 |
| Line Range Detection Threshold, falling | VLL | 1.6 | 1.7 | 1.8 | V | Vsense falling | 6 |
| Line Range Detection Hysteresis | VHL(hyst) | 400 | 500 | 600 | mV | 6 | |
| Blanking Time for Line Range Detection | THL(blank) | 15 | 25 | 35 | ms | 6 | |
| Brown-Out Pin Bias Current | IBO(bias) | -250 | 250 | nA | Vsense = VBOH | 6 | |
| Power Supply Input (absolute maximum) | VCC | -0.3 | 35 | V | Pin 7 | 3 | |
| Vsense pin voltage (absolute maximum) | Vsense | -0.3 | 10 | V | Pin 2 | 3 | |
| FFcontrol pin voltage (absolute maximum) | FFcontrol | -0.3 | 10 | V | Pin 3 | 3 | |
| CS/ZCD input voltage (absolute maximum) | CS/ZCD | -0.3 | 35 | V | Pin 4 | 3 | |
| CS/ZCD injected current (absolute maximum) | 5 | mA | Current injected to pin 4 | 3 | |||
| Driver Current (absolute maximum) | -500 | 800 | mA | Pin 6 | 3 | ||
| Feedback pin voltage (absolute maximum) | FB | -0.3 | 10 | V | Pin 8 | 3 | |
| Maximum Power Dissipation | PD | 550 | mW | TA = 70°C | 3 | ||
| Thermal Resistance Junction to Air | RθJA | 145 | °C/W | 3 | |||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 3 |
CAD (KiCad official)
- Symbol:
NCP1611ADR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp1611adr2g-etched.step/ncp1611adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp1611adr2g.step/ncp1611adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (29 pp, sha256
e9e46309484a984f, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).