# NCP1562BDR2G

**onsemi** · AC-DC Controllers And Regulators · SO-16

NCP1562BDR2G from onsemi, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vin | power_in | Connect the input line voltage directly to this pin to enable the internal startup regulator; maximum input voltage is 100 V. |
| 2 | UVOV | input | Scaled-down input supply sense for undervoltage (below 2.0 V) and overvoltage (above 3.0 V) detection, with 100 mV hysteresis on both detectors. |
| 3 | FF | input | An external R-C divider from the input line generates the feedforward ramp that sets the duty cycle for line regulation, and an internal pulldown discharges the capacitor every cycle. |
| 4 | CS | input | Overcurrent sense input that triggers cycle-by-cycle current limit when CS exceeds 0.2 V (0.5 V in the NCP1562B). |
| 5 | GND | power_in | Control circuit ground, and all control and timing components connected to it should have the shortest possible loop to this pin. |
| 6 | RTCT | passive | An external RT-CT divider from VREF sets the operating frequency and maximum duty cycle of OUT1, with a maximum operating frequency of 1.0 MHz. |
| 7 | SYNC | bidirectional | Bidirectional frequency synchronization pin that lets two NCP1562 devices synchronize together (the lower-frequency device becomes the slave) or synchronize to an external signal. |
| 8 | VREF | power_out | Precision 5.0 V reference with a maximum output current of 5.0 mA, which must be bypassed with a capacitor between 0.047 mF and 1.0 mF. |
| 9 | VEA | input | Error amplifier input compared to the feedforward ramp, with a series diode and resistor offset and an internal pullup that allows direct connection to an optocoupler. |
| 10 | SS | passive | Soft-start capacitor pin charged by a 10 mA source, with a steady-state voltage of approximately 3.8 V and controlled discharge at 100 mA after a fault. |
| 11 | tD | passive | An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2 transitions. |
| 12 | CSKIP | passive | Cycle-skip timing capacitor pin: CCSKIP is charged at 100 mA after a current-limit fault and the converter enters soft-stop at 3.0 V, re-enabling at 0.5 V. |
| 13 | OUT2 | output | Secondary PWM output for an active clamp/reset switch or synchronous rectifier, with 12 Ω typical source and sink resistance and designed to handle up to 1.0 A. |
| 14 | PGND | power_in | Ground connection for OUT1 and OUT2, to be tied to the power stage return with a short loop. |
| 15 | OUT1 | output | Main PWM output with 4.0 Ω typical source and 2.5 Ω typical sink resistance, designed to handle up to 2.5 A. |
| 16 | VAUX | power_in | Positive input supply tied to an external storage capacitor; outputs are enabled at about 10.3 V and disabled at 7.0 V during startup, and the device is powered from an auxiliary winding in normal operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SO-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Startup Threshold/VAUX Regulation Peak (VAUX Increasing) | VAUX(on) | 9.65 | 10.3 | 10.97 | V | VAUX increasing | 6 |
| Operating VAUX Valley Voltage | VAUX(off1) | 7.42 | 8 | 8.48 | V |  | 6 |
| Minimum Operating VAUX Valley Voltage after Turn-On | VAUX(off2) | 6.5 | 7 | 7.42 | V | VUVOV = 2.3 V, VEA = 0 V | 6 |
| Minimum Startup Voltage (Pin 1) | Vstart(min) |  |  | 23.2 | V | IAUX = 1.0 mA, VAUX = VAUX(on), 0.2 V | 6 |
| Inhibit Bias Current | Iinhibit | 70 | 170 | 300 | mA | VAUX = 0 V | 6 |
| Startup Circuit Output Current | Istart1 | 7.16 | 9.3 | 11.3 | mA | VAUX = Vinhibit + 0.2 V | 6 |
| Startup Circuit Output Current | Istart2 | 4.03 | 6.1 | 8.1 | mA | VAUX = VAUX(on), 0.2 V | 6 |
| Startup Circuit Off-State Leakage Current (TJ = -40 to 125 °C; 25 °C row omitted, see review) | Istart(off) |  |  | 100 | mA | Vin = 200 V, VUVOV = 0 V; TJ = -40 to 125 °C | 6 |
| Startup Circuit Breakdown Voltage | VBR(DS) | 100 |  |  | V | Istart(off) = 50 mA, TJ = 125 °C (Note 3) | 6 |
| Auxiliary Supply Current after VAUX Turn-On, Outputs Disabled | IAUX1 |  | 3 | 3.6 | mA | Outputs disabled, VUVOV = 0 V, VEA = 0 V | 6 |
| Auxiliary Supply Current after VAUX Turn-On | IAUX2 |  | 4.2 | 4.94 | mA |  | 6 |
| Auxiliary Supply Current after VAUX Turn-On, Outputs Enabled | IAUX3 |  | 5.5 | 7 | mA | Outputs enabled, VEA = 4.0 V | 6 |
| Undervoltage Threshold (Vin Increasing) | VUV | 1.979 | 2.05 | 2.116 | V |  | 6 |
| Undervoltage Hysteresis | VUV(H) | 0.074 | 0.093 | 0.118 | V |  | 6 |
| Overvoltage Threshold (Vin Increasing) | VOV | 2.8 | 2.95 | 3.1 | V |  | 6 |
| Overvoltage Hysteresis | VOV(H) | 0.075 | 0.093 | 0.127 | V |  | 6 |
| Offset Current | Ioffset(UVOV) | 38 | 48 | 58 | mA | VUVOV = 2.8 V | 6 |
| Peak Voltage (Volt-Second Clamp) | VFF(peak) | 2.8 | 3 | 3.2 | V |  | 6 |
| Discharge Current | IFF(D) | 8.5 |  |  | mA | VFF = 0.5 V, VSS = 0 V | 6 |
| Offset Voltage | Voffset(FF) | 0.118 | 0.185 | 0.268 | V | VFF = 0 V, Ramp Down VSS | 6 |
| Feedforward Offset Minus Soft-Stop Reset Voltage | Δ(FF--SS) | 7 | 70 | 183 | mV |  | 6 |
| Cycle-by-Cycle Threshold Voltage, NCP1562B | VILIM | 472 | 495 | 512 | mV | Vout = 10 V | 7 |
| Propagation Delay to Output (TJ = -40 to 125 °C; 25 °C row omitted, see review) | tILIM |  |  | 110 | ns | VCS = VILIM to 1.0 V, LEB Disabled, Vout = 10 V | 7 |
| Cycle Skip Charge Current | ICSKIP(C) | 70 | 90 | 111 | mA | VCSKIP = 1.25 V | 7 |
| Cycle Skip Discharge Current | ICSKIP(D) | 6.5 | 8.6 | 11 | mA | VCSKIP = 1.25 V | 7 |
| Upper Threshold Voltage | VCSKIP(peak) | 2.83 | 3.03 | 3.24 | V | Ramp up VCSKIP, VCS = 1.0 V | 7 |
| Lower Threshold Voltage | VCSKIP(valley) | 0.39 | 0.465 | 0.52 | V | Ramp down VCSKIP | 7 |
| Output Voltage | VREF | 4.9 | 5 | 5.1 | V | IREF = 0 mA | 7 |
| Frequency | fOSC | 222 | 246 | 272.2 | kHz | TJ = 25 °C | 7 |
| Frequency | fOSC | 211.2 |  | 277.2 | kHz | TJ = -40 to 125 °C | 7 |
| Maximum Operating Frequency | fMAX | 1 |  |  | MHz | Note 4 | 7 |
| Duty Cycle | D | 58.5 | 62 | 64.7 | % | RD = 25 kΩ | 7 |
| Adjustable Maximum Duty Cycle | DMAX | 85 |  |  | % | Note 4 | 7 |
| Sync Threshold Voltage | VSYNC | 3.5 |  |  | V | Note 5 | 8 |
| Soft-Start Charge Current | ISS(C) | 8.3 | 10.2 | 13.1 | mA | VSS = 1.6 V | 8 |
| Overlap Time Delay, Leading | tD(leading) | 37 | 45 |  | ns | Tested at 50% of waveform | 8 |
| Output Voltage, Low State | VOL |  |  | 0.25 | V | IOUT = 0 mA, Note 5 | 8 |
| Output Voltage, High State | VOH | 11.8 |  |  | V | IOUT = 0 mA, Note 5 | 8 |
| Drive Resistance (FT ONLY), OUT1 Sink | RSNK1 |  | 2.8 | 3.6 | Ω | TJ = 25 °C; VRTCT = 4.0 V, Vout1 = 1.0 V | 8 |
| Drive Resistance (FT ONLY), OUT1 Sink | RSNK1 |  |  | 5.03 | Ω | TJ = -40 to 125 °C; VRTCT = 4.0 V, Vout1 = 1.0 V | 8 |
| Drive Resistance (FT ONLY), OUT1 Source | RSRC1 |  | 4.7 | 5.75 | Ω | TJ = 25 °C; VRTCT = 2.5 V, Vout1 = 11 V | 8 |
| Drive Resistance (FT ONLY), OUT1 Source | RSRC1 |  |  | 7.45 | Ω | TJ = -40 to 125 °C; VRTCT = 2.5 V, Vout1 = 11 V | 8 |
| Drive Resistance (FT ONLY), OUT2 Sink | RSNK2 |  | 11.4 | 12.7 | Ω | TJ = 25 °C; VRTCT = 4.0 V, Vout2 = 1.0 V | 8 |
| Drive Resistance (FT ONLY), OUT2 Sink | RSNK2 |  |  | 20 | Ω | TJ = -40 to 125 °C; VRTCT = 4.0 V, Vout2 = 1.0 V | 8 |
| Drive Resistance (FT ONLY), OUT2 Source | RSRC2 |  | 11.6 | 13.5 | Ω | TJ = 25 °C; VRTCT = 2.5 V, Vout2 = 11 V | 8 |
| PWM Comparator Lower Input Threshold | VEA(L) | 0.48 | 0.83 | 1.04 | V |  | 8 |
| Line Voltage | Vin |  |  | 100 | V |  | 5 |
| Auxiliary Supply, OUT1, OUT2 | VAUX, Voutx |  |  | 20 | V |  | 5 |
| All Other Inputs/Outputs Voltage | VIO |  |  | 10 | V |  | 5 |
| All Other Inputs/Outputs Current | IIO |  |  | 5 | mA |  | 5 |
| 5.0 V Reference Output Current | IREF |  |  | 10 | mA |  | 5 |
| 5.0 V Reference Output Voltage | VREF | -0.3 |  | 6 | V |  | 5 |
| OUT1 Peak Output Current | Iout1 |  |  | 2.5 | A | D = 2% | 5 |
| OUT2 Peak Output Current | Iout2 |  |  | 1 | A | D = 2% | 5 |
| Operating Junction Temperature | TJ | -40 |  | 125 | °C |  | 5 |
| Storage Temperature Range | Tstg | -55 |  | 150 | °C |  | 5 |
| Power Dissipation, D Suffix SO-16 (Case 751B) | PD |  |  | 0.95 | W | TA = 25 °C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad | 5 |
| Thermal Resistance, Junction to Ambient, D Suffix SO-16, 0.36 sq in | RθJA |  |  | 120 | °C/W | 2.0 Oz Cu Printed Circuit Copper Clad, 0.36 Sq In | 5 |
| Thermal Resistance, Junction to Ambient, D Suffix SO-16, 1.0 sq in | RθJA |  |  | 105 | °C/W | 2.0 Oz Cu Printed Circuit Copper Clad, 1.0 Sq In | 5 |
| Oscillator timing resistor RT minimum | RT | 6 |  |  | kΩ | RT should not be less than 6.0 kΩ (text, not a table) | 21 |

## CAD (KiCad official)

- Symbol: `NCP1562BDR2G`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files: `ncp1562bdr2g-etched.step` / `ncp1562bdr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp1562bdr2g.step` / `ncp1562bdr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588935061953921024) (26 pp, sha256 `ef52195bf3d19e16`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ncp1562bdr2g-datasheet.pdf)