component
NCP1562ADR2G
Public Made by Adomby adom
onsemi DC-DC Controllers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCP1562ADR2G
onsemi · DC-DC Controllers · SO-16
NCP1562ADR2G from onsemi, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vin | power_in | Connect the input line voltage directly to this pin to enable the internal startup regulator, with a maximum input voltage of 100 V and a typical charge current of 10 mA. |
| 2 | UVOV | input | Scaled input supply voltage used for undervoltage detection below 2.0 V and overvoltage detection above 3.0 V, with 100 mV hysteresis on both detectors. |
| 3 | FF | input | External R-C divider from the input line generates the feedforward ramp that sets the PWM duty cycle for line regulation, and an internal pulldown discharges the capacitor every cycle. |
| 4 | CS | input | Overcurrent sense input that triggers cycle-by-cycle current limit when the voltage exceeds 0.2 V (0.5 V in the NCP1562B) and includes leading edge blanking. |
| 5 | GND | power_in | Control circuit ground that all control and timing components should connect to through the shortest possible loop. |
| 6 | RTCT | passive | An external RT-CT divider from VREF sets the operating frequency and maximum duty cycle of OUT1 across a sawtooth ramp between 2.0 V and 3.0 V, with a maximum frequency of 1.0 MHz. |
| 7 | SYNC | bidirectional | Bidirectional frequency synchronization pin that allows two NCP1562 devices to synchronize, with the lower frequency device becoming the slave, and that can also lock to an external signal. |
| 8 | VREF | power_out | Precision 5.0 V reference with a maximum output current of 5.0 mA, which requires a bypass capacitor between 0.047 µF and 1.0 µF. |
| 9 | VEA | input | Input for the external error amplifier signal, compared to the feedforward ramp after a series diode and resistor offset, with an internal pullup resistor allowing direct connection to an optocoupler. |
| 10 | SS | passive | A 10 µA current source charges the external soft-start capacitor to limit duty cycle during startup, with steady-state voltage of approximately 3.8 V and a 100 µA discharge on faults. |
| 11 | tD | passive | An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2 transitions. |
| 12 | CSKIP | passive | The external capacitor on this pin sets the cycle skip fault detection time and the disable time, with the converter entering soft-stop once the capacitor reaches 3.0 V. |
| 13 | OUT2 | output | Secondary PWM output for driving an active clamp/reset switch or synchronous rectifier, with source and sink resistances of 12 Ω (typ.) and a designed handling limit of 1.0 A. |
| 14 | PGND | power_in | Ground connection for OUT1 and OUT2 that should be tied to the power stage return with a short loop. |
| 15 | OUT1 | output | Main PWM output with source resistance of 4.0 Ω (typ.) and sink resistance of 2.5 Ω (typ.), designed to handle up to 2.5 A. |
| 16 | VAUX | power_in | Positive supply input connected to an external storage capacitor, where outputs are enabled at approximately 10.3 V and disabled when VAUX falls to 7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SO-16 |
| Category | Power Management ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Line Voltage | Vin | 100 | V | 5 | |||
| Auxiliary Supply, OUT1, OUT2 | VAUX, Voutx | 20 | V | 5 | |||
| All Other Inputs/Outputs Voltage | VIO | 10 | V | 5 | |||
| 5.0 V Reference Output Voltage | VREF | -0.3 | 6 | V | 5 | ||
| OUT1 Peak Output Current | Iout1 | 2.5 | A | D = 2% | 5 | ||
| OUT2 Peak Output Current | Iout2 | 1 | A | D = 2% | 5 | ||
| Operating Junction Temperature | TJ | -40 | 125 | C | 5 | ||
| Power Dissipation, D Suffix SO-16 | PD | 0.95 | W | TA = 25 C, 2.0 Oz Cu, 1.0 Sq Inch PCB copper clad | 5 | ||
| Thermal Resistance Junction to Ambient, D Suffix SO-16, 0.36 Sq In | RJA | 120 | C/W | 2.0 Oz Cu PCB copper clad, 0.36 Sq In | 5 | ||
| Thermal Resistance Junction to Ambient, D Suffix SO-16, 1.0 Sq In | RJA | 105 | C/W | 2.0 Oz Cu PCB copper clad, 1.0 Sq In | 5 | ||
| VAUX Startup Threshold/VAUX Regulation Peak (VAUX Increasing) | VAUX(on) | 9.65 | 10.3 | 10.97 | V | 6 | |
| Operating VAUX Valley Voltage | VAUX(off1) | 7.42 | 8 | 8.48 | V | 6 | |
| Minimum Operating VAUX Valley Voltage after Turn-On | VAUX(off2) | 6.5 | 7 | 7.42 | V | VUVOV = 2.3 V, VEA = 0 V | 6 |
| Inhibit Threshold Voltage | Vinhibit | 1.15 | 1.5 | V | 6 | ||
| Minimum Startup Voltage (Pin 1) | Vstart(min) | 23.2 | V | IAUX = 1.0 mA, VAUX = VAUX(on), 0.2 V | 6 | ||
| Inhibit Bias Current | Iinhibit | 70 | 170 | 300 | µA | VAUX = 0 V | 6 |
| Startup Circuit Output Current | Istart1 | 7.16 | 9.3 | 11.3 | mA | VAUX = Vinhibit + 0.2 V | 6 |
| Startup Circuit Output Current | Istart2 | 4.03 | 6.1 | 8.1 | mA | VAUX = VAUX(on), 0.2 V | 6 |
| Startup Circuit Off-State Leakage Current (Vin = 200 V, VUVOV = 0 V) | Istart(off) | 25 | µA | TJ = 25 C | 6 | ||
| Startup Circuit Off-State Leakage Current (Vin = 200 V, VUVOV = 0 V) | Istart(off) | 50 | 100 | µA | TJ = -40 C to 125 C | 6 | |
| Startup Circuit Breakdown Voltage | VBR(DS) | 100 | V | Istart(off) = 50 µA, TJ = 125 C | 6 | ||
| Auxiliary Supply Current after VAUX Turn-On (Outputs Disabled) | IAUX1 | 3 | 3.6 | mA | VUVOV = 0 V, VEA = 0 V | 6 | |
| Auxiliary Supply Current after VAUX Turn-On (Outputs Enabled) | IAUX2 | 4.2 | 4.94 | mA | VEA = 4.0 V | 6 | |
| Auxiliary Supply Current after VAUX Turn-On (Outputs Enabled) | IAUX3 | 5.5 | 7 | mA | VEA = 4.0 V | 6 | |
| Undervoltage Threshold (Vin Increasing) | VUV | 1.979 | 2.05 | 2.116 | V | 6 | |
| Undervoltage Hysteresis | VUV(H) | 0.074 | 0.093 | 0.118 | V | 6 | |
| Overvoltage Threshold (Vin Increasing) | VOV | 2.8 | 2.95 | 3.1 | V | 6 | |
| Overvoltage Hysteresis | VOV(H) | 0.075 | 0.093 | 0.127 | V | 6 | |
| Offset Current | Ioffset(UVOV) | 38 | 48 | 58 | µA | VUVOV = 2.8 V | 6 |
| Offset Current Turn ON Threshold | Voffset(UVOV) | 2.4 | 2.6 | 2.8 | V | 5%, Ioffset(UVOV) = 40 µA | 6 |
| Peak Voltage (Volt-Second Clamp) | VFF(peak) | 2.8 | 3 | 3.2 | V | 6 | |
| Discharge Current | IFF(D) | 8.5 | mA | VFF = 0.5 V, VSS = 0 V | 6 | ||
| Offset Voltage | Voffset(FF) | 0.118 | 0.185 | 0.268 | V | VFF = 0 V, Ramp Down VSS | 6 |
| Feedforward Offset Minus Soft-Stop Reset Voltage | (FF-SS) | 7 | 70 | 183 | mV | 6 | |
| Cycle-by-Cycle Threshold Voltage, NCP1562A | VILIM | 191 | 203 | 217 | mV | Vout = 10 V | 7 |
| Propagation Delay to Output | tILIM | 78 | ns | VCS = VILIM to 1.0 V, LEB Disabled, Vout = 10 V, TJ = 25 C | 7 | ||
| Propagation Delay to Output | tILIM | 90 | 110 | ns | VCS = VILIM to 1.0 V, LEB Disabled, Vout = 10 V, TJ = -40 C to 125 C | 7 | |
| Blanking Time | tLEB | 50 | 80 | 110 | ns | 7 | |
| VEA Threshold the Disables LEB | VLEB(dis) | 4.1 | V | Measured together with tLEB | 7 | ||
| Charge Current | ICSKIP(C) | 70 | 90 | 111 | µA | VCSKIP = 1.25 V | 7 |
| Discharge Current | ICSKIP(D) | 6.5 | 8.6 | 11 | µA | VCSKIP = 1.25 V | 7 |
| Upper Threshold Voltage | VCSKIP(peak) | 2.83 | 3.03 | 3.24 | V | Ramp up VCSKIP, VCS = 1.0 V | 7 |
| Lower Threshold Voltage | VCSKIP(valley) | 0.39 | 0.465 | 0.52 | V | Ramp down VCSKIP | 7 |
| VREF Output Voltage | VREF | 4.9 | 5 | 5.1 | V | IREF = 0 mA | 7 |
| Discharge Current | IREF(D) | 3.8 | mA | VUVOV = 0 V, VREF = 2.5 V | 7 | ||
| Oscillator Frequency | fOSC | 222 | 246 | 272.2 | kHz | TJ = 25 C | 7 |
| Oscillator Frequency | fOSC | 211.2 | 277.2 | kHz | TJ = -40 C to 125 C | 7 | |
| Maximum Operating Frequency | fMAX | 1 | MHz | 7 | |||
| Duty Cycle | D | 58.5 | 62 | 64.7 | % | RD = 25 k | 7 |
| Adjustable Maximum Duty Cycle | DMAX | 85 | % | 7 | |||
| Output Pulse Width | tO(SYNC) | 70 | 110 | ns | 8 | ||
| Sync Threshold Voltage | VSYNC | 3.5 | V | 8 | |||
| Maximum Sync Frequency | fSYNC | 1 | MHz | 8 | |||
| Charge Current | ISS(C) | 8.3 | 10.2 | 13.1 | µA | VSS = 1.6 V | 8 |
| Discharge Current | ISS(D) | 72 | 95 | 115 | µA | VUVOV = 0 V, VSS = 1.6 V | 8 |
| Overlap Time Delay Leading | tD(leading) | 37 | 45 | ns | Tested at 50% of Waveform | 8 | |
| Overlap Time Delay Trailing | tD(trailing) | 72 | 90 | ns | Tested at 50% of Waveform | 8 | |
| Output Voltage Low State | VOL | 0.25 | V | IOUT = 0 mA | 8 | ||
| Output Voltage High State | VOH | 11.8 | V | IOUT = 0 mA | 8 | ||
| Lower Input Threshold | VEA(L) | 0.48 | 0.83 | 1.04 | V | 8 |
CAD (KiCad official)
- Symbol:
NCP1562ADR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
ncp1562adr2g-etched.step/ncp1562adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp1562adr2g.step/ncp1562adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (29 pp, sha256
cbe87bd5648976e1, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).