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NCP1397BDR2G

onsemi · AC-DC Controllers and Regulators · SOIC-16

NCP1397BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CSS(dis) passive Soft-start capacitor discharge pin. Connect to the external soft-start capacitor to reset (discharge) it before startup or during overload conditions so the next startup ramp begins from zero.
2 Fmax passive Maximum frequency clamp. A resistor to this pin sets the upper frequency excursion of the VCO (VCO range up to 500 kHz).
3 Ctimer passive Fault timer duration. An external capacitor to GND sets the duration the controller tolerates a fault at the Fault pin before shutting down.
4 Rt passive Minimum frequency clamp. A resistor to this pin sets the minimum oscillator frequency reached when VFB = 1 V (lower limit of the VCO sweep, typically ≥50 kHz).
5 BO input Brown-out detection input. Senses a scaled image of the bulk voltage; when the pin is driven above Vlatch (~4 V) the controller fully latches off, providing brown-out and PFC-association protection.
6 FB input Feedback input. Injecting current (typically from an optocoupler in common-collector configuration) into this pin increases the oscillation frequency up to Fmax, providing loop regulation.
7 DT passive Deadtime adjustment. A single resistor to GND sets the half-bridge dead-time between high-side and low-side conduction, adjustable from ~100 ns to 2 µs to prevent shoot-through.
8 Skip/Disable input Skip or Disable input. Pulling low enters skip/disable; upon release a clean soft-start sequence occurs if VFB < 0.3 V, otherwise the IC restarts without soft-start (skip-cycle mode).
9 Fault input Fault detection input. When asserted above the first threshold the external timer (Ctimer) starts counting down and shuts down the controller; the soft-start discharge switch is simultaneously activated so operating frequency rises to protect the power stage. A second higher threshold (~1.5 V) latches the IC off permanently on the 'B' variant (NCP1397B).
10 GND power_in Analog ground reference for the controller and low-side driver return.
11 Mlower output Low-side gate driver output. Drives the gate of the lower half-bridge MOSFET, referenced to GND, with 1 A sink / 0.5 A source peak capability.
12 VCC power_in Controller supply pin. Accepts up to 20 V; typical startup current is 300 µA. Decouple with a local ceramic capacitor to GND.
13 NC unconnected Pin 13 is omitted from the package (SO-16 'Less Pin 13'). Its absence increases the creepage distance between the low-voltage (VCC, pin 12) and high-voltage floating (HB, pin 14) sections.
14 HB passive Half-bridge switching node connection. Return/reference for the high-side driver and bootstrap capacitor; connects to the source of the upper MOSFET / drain of the lower MOSFET (switching node up to 600 V).
15 Mupper output High-side gate driver output. Drives the gate of the upper half-bridge MOSFET, floating between HB and Vboot; 1 A sink / 0.5 A source peak capability.
16 Vboot power_in Bootstrap supply pin for the high-side floating driver. Connect a bootstrap capacitor between Vboot and HB (charged from VCC via an external bootstrap diode) to supply the upper gate driver.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category PMIC
Pins 16

Ordering variants

  • NCP1397BDR2GADR2G
  • NCP1397BDR2G

CAD (KiCad official)

  • Symbol: NCP1397BDR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (None pp, sha256 cee5e90dc431cbdf, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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