component
NCP1393BDR2G
Public Made by Adomby adom
onsemi Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCP1393BDR2G
onsemi · Gate Drivers · SOIC-8
NCP1393BDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supplies the driver, which accepts up to 16 V as limited by the internal zener clamp (VCCclamp 15.4 to 17.5 V at 20 mA); current into VCC must be limited externally when supplied above the clamp voltage. |
| 2 | Rt | passive | Timing resistor pin; a resistor between this pin and GND sets the operating frequency, and the capacitance directly connected to it must stay under 100 pF. |
| 3 | BO | input | Brown-out pin that detects low input voltage and blocks output pulses below the brown-out level; when brought above Vlatch (2 V typical) it fully latches off the driver. |
| 4 | GND | power_in | IC ground reference for the controller and the internal zener clamp between VCC and GND. |
| 5 | Mlower | output | Low-side driver output that drives the lower-side MOSFET, with a 1 A sink / 0.5 A source drive capability and a fixed dead time of about 0.6 µs. |
| 6 | HB | passive | Half-bridge connection to the half-bridge output node; the high-voltage bridge pin is rated −1 V to +600 V. |
| 7 | Mupper | output | High-side driver output that drives the higher-side MOSFET, referenced to the HB pin and limited to Vbridge − 0.3 V to Vboot + 0.3 V. |
| 8 | Vboot | power_in | Bootstrap pin, the floating supply terminal for the upper stage, rated 0 to 20 V above Vbridge. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High Voltage Bridge Pin (Pin 6) | Vbridge | -1 | 600 | V | 4 | ||
| Floating Supply Voltage | Vboot − Vbridge | 0 | 20 | V | 4 | ||
| Allowable Output Slew Rate | dVbridge/dt | 50 | V/ns | 4 | |||
| Maximum Current that Can Flow into VCC Pin (Pin 1), (Note 1) | ICC | 20 | mA | 4 | |||
| Rt Pin Voltage | V_Rt | -0.3 | 5 | V | 4 | ||
| Maximum Voltage, All Pins (Except Pins 4 and 5) | -0.3 | 10 | V | All pins except pins 4 and 5 | 4 | ||
| ESD Capability, Human Body Model (All Pins Except Pins 1, 6, 7 and 8) | 2 | kV | All pins except pins 1, 6, 7 and 8 | 4 | |||
| ESD Capability, Machine Model (All Pins Except Pins 1, 6, 7 and 8) | 200 | V | All pins except pins 1, 6, 7 and 8 | 4 | |||
| Storage Temperature Range | -60 | 150 | °C | 4 | |||
| Turn-On Threshold Level, VCC Going Up | VCCON | 10 | 11 | 12 | V | VCC going up | 5 |
| Minimum Operating Voltage after Turn-On | VCCmin | 8 | 9 | 10 | V | 5 | |
| Startup Voltage on the Floating Section | VbootON | 7.8 | 8.8 | 9.8 | V | 5 | |
| Cutoff Voltage on the Floating Section | Vbootmin | 7 | 8 | 9 | V | 5 | |
| Startup Current, 0°C ≤ Tamb ≤ +125°C | ICC | 50 | µA | VCC < VCCON, 0°C ≤ Tamb ≤ +125°C | 5 | ||
| Startup Current, −40°C ≤ Tamb < 0°C | ICC | 65 | µA | VCC < VCCON, −40°C ≤ Tamb < 0°C | 5 | ||
| Consumption During PFC Delay Period, 0°C ≤ Tamb ≤ +125°C | ICC4 | 400 | µA | 0°C ≤ Tamb ≤ +125°C | 5 | ||
| Consumption During PFC Delay Period, −40°C ≤ Tamb < 0°C | ICC4 | 470 | µA | −40°C ≤ Tamb < 0°C | 5 | ||
| VCC Zener Clamp Voltage | VCCclamp | 15.4 | 16 | 17.5 | V | @ 20 mA | 5 |
| Minimum Switching Frequency | FSW min | 24.25 | 25 | 25.75 | kHz | Rt = 35 k on Pin 2, DT = 600 ns | 5 |
| Maximum Switching Frequency | FSW max | 208 | 245 | 282 | kHz | Rt = 3.5 k on Pin 2, DT = 600 ns | 5 |
| Reference Voltage for all Current Generations | Vref RT | 3.33 | 3.5 | 3.67 | V | 5 | |
| Operating Duty Cycle Symmetry | DC | 48 | 50 | 52 | % | 5 | |
| Dead-Time (Measured Between 50% of Rise and Fall Edge) | T_dead | 540 | 610 | 720 | ns | Measured Between 50% of Rise and Fall Edge | 5 |
| Leakage Current on High Voltage Pins to GND (600 Vdc) | IHV_Leak | 5 | µA | 600 Vdc | 5 | ||
| Brown-Out Level | VBO | 0.95 | 1 | 1.05 | V | 5 | |
| Hysteresis Current, Vpin3 < VBO | IBO | 15.6 | 18.2 | 20.7 | µA | Vpin3 < VBO | 5 |
| Latching Voltage on BO Pin | Vlatch | 1.9 | 2 | 2.1 | V | 5 | |
| Temperature Shutdown | TSD | 140 | °C | 5 | |||
| Maximum capacitance directly connected to Pin 2 | 100 | pF | Directly connected to Pin 2; must be under 100 pF | 5 | |||
| VCC Level at which the Internal Logic gets Reset | VCCreset | 6.5 | V | 5 | |||
| Internal IC Consumption, No Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz | ICC1 | 2.2 | mA | No Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz | 5 | ||
| Internal IC Consumption, 1 nF Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz | ICC2 | 3.4 | mA | 1 nF Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz | 5 | ||
| Consumption in Fault Mode | ICC3 | 2.56 | mA | Drivers Disabled, VCC > VCC(min), RT = 3.5 k | 5 | ||
| Internal IC Consumption, No Output Load on Pin 8/7 | Iboot1 | 0.3 | mA | No Output Load on Pin 8/7 FWS = 100 kHz | 5 | ||
| Internal IC Consumption, 1 nF Output Load on Pin 8/7 | Iboot2 | 1.44 | mA | 1 nF Output Load on Pin 8/7 FWS = 100 kHz | 5 | ||
| Consumption in Fault Mode (Drivers Disabled, Vboot > Vbootmin) | Iboot3 | 0.1 | mA | Drivers Disabled, Vboot > Vbootmin | 5 | ||
| Internal Resistance Discharging Csoft-start | Rtdischarge | 500 | Ω | 5 | |||
| Output Voltage Rise Time | Tr | 40 | ns | @ CL = 1 nF, 10−90% of Output Signal | 5 | ||
| Output Voltage Fall Time | Tf | 20 | ns | @ CL = 1 nF, 10−90% of Output Signal | 5 | ||
| Source Resistance | ROH | 12 | Ω | 5 | |||
| Sink Resistance | ROL | 5 | Ω | 5 | |||
| Brown-Out Input Bias Current | IBObias | 0.01 | µA | 5 | |||
| Propagation Delay Before Drivers are Stopped | EN Delay | 20 | µs | 5 | |||
| Delay Before Any Driver Restart − PFC Delay | 100 | ms | 5 | ||||
| Hysteresis | TSDhyste | 30 | °C | 5 | |||
| Thermal Resistance Junction-to-Air | RJA | 178 | °C/W | IC soldered on 50 mm² copper 35 µm | 4 | ||
| Thermal Resistance Junction-to-Air | RJA | 147 | °C/W | IC soldered on 200 mm² copper 35 µm | 4 |
CAD (KiCad official)
- Symbol:
NCP1393BDR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp1393bdr2g-etched.step/ncp1393bdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp1393bdr2g.step/ncp1393bdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (16 pp, sha256
321a1cc875b8d374, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).