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NCP1380CDR2G

Public Made by Adom

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onsemi AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)ncp1380cdr2gfactory-2.0.0extractor-text
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Contents

README

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NCP1380CDR2G

onsemi · AC-DC Controllers And Regulators · SOIC-8

NCP1380CDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ZCD input Zero-crossing detection pin connected to the auxiliary winding to detect the core reset event, and injecting a negative voltage smaller than 0.3 V on it performs over power protection (OPP).
2 FB input Feedback pin where an optocoupler collector is hooked to allow regulation.
3 CS input Current sense pin that monitors the primary peak current.
4 GND power_in Controller ground.
5 DRV output Driver output to an external MOSFET, rated for +500 mA source / −800 mA sink peak capability.
6 VCC power_in Supply pin for the controller, connected to an external auxiliary voltage; extended VCC range operation is up to 28 V.
7 Fault input For version C, combines overvoltage and brown-out protection by observing the HV rail; pulling it down with an NTC or up with a zener latches the controller on an overvoltage event.
8 CT passive Timing capacitor connection; a capacitor here sets the timing in foldback mode.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Startup Threshold (VCC(on)) VCC(on) 16 17 18 V VCC increasing 6
Minimum Operating Voltage (VCC(off)) VCC(off) 8.3 9 9.4 V VCC decreasing 6
Hysteresis VCC(on) − VCC(off) VCC(HYS) 7.2 8 9.2 V 6
Clamped VCC when latched-off VCC(latch) 6.2 7.2 8.2 V 6
Startup current, FB pin open ICC(start) 10 20 µA VCC = VCC(on) − 0.5 V 6
Current that discharges VCC when the controller gets latched ICC(disch) 3 4 5 mA VCC = 12 V 6
Current into VCC that keeps the controller latched ICC(latch) 30 µA VCC = VCC(latch) 6
Current Sense Voltage Threshold VILIM 0.76 0.8 0.84 V VFB = 4 V, VCS increasing 6
Leading Edge Blanking Duration for VILIM tLEB 210 275 330 ns Minimum on time minus tILIM 6
Input Bias Current Ibias -2 2 µA DRV high 6
Propagation Delay VCS > VILIM to DRV turn-off tILIM 125 175 ns VCS > VILIM to DRV turn-off 6
Percentage of maximum peak current level at which VCO takes over Ipeak(VCO) 15.4 17.5 19.6 % VFB = 0.4 V, VCS increasing 6
Setpoint decrease for OPP VOPP(MAX) 35 37.5 40 % VZCD = −300 mV, VFB = 4 V, VCS increasing 7
Threshold for immediate fault protection activation VCS(stop) 1.125 1.2 1.275 V 7
Rise Time (10% to 90%) tr 40 75 ns CDRV = 1 nF, VDRV from 0 to 12 V 7
Fall Time (90% to 10%) tf 25 60 ns CDRV = 1 nF, VDRV from 0 to 12 V 7
DRV Low Voltage VDRV(low) 8.4 9.1 V VCC = VCC(off) + 0.2 V, CDRV = 1 nF, RDRV = 33 kΩ 7
DRV High Voltage VDRV(high) 10.5 13 15.5 V VCC = VCC(MAX), CDRV = 1 nF 7
ZCD threshold voltage VZCD(TH) 35 55 90 mV VZCD decreasing 7
ZCD hysteresis VZCD(HYS) 15 35 55 mV VZCD increasing 7
Input clamp voltage, high state VCH 8 10 12 V High state, Ipin1 = 3.0 mA 7
Input clamp voltage, low state VCL -0.9 -0.7 -0.3 V Low state, Ipin1 = −2.0 mA 7
Propagation Delay (demagnetization input) tDEM 150 250 ns VZCD decreasing from 4 V to −0.3 V 7
Blanking delay after on-time tBLANK 2.3 3.15 4 µs 7
Timeout after last demag transition during soft-start toutSS 28 41 54 ms During soft-start 7
Timeout after last demag transition after the end of soft-start tout 5 5.9 6.7 ms After the end of soft-start 7
Maximum voltage on CT pin VCT(MAX) 5.15 5.4 5.65 V VFB < VFB(TH) 7
Source current ICT 18 20 22 µA VCT = 0 V 7
Minimum voltage on CT pin, discharge switch activated VCT(MIN) 90 mV 7
Internal pullup resistor RFB(pullup) 15 18 22 kΩ 7
Pin FB to current setpoint division ratio Iratio 3.8 4 4.2 7
FB pin threshold under which CT is clamped to VCT(MAX) VFB(TH) 0.26 0.3 0.34 V 7
FB voltage where 1st valley ends and 2nd valley starts VH2D 1.316 1.4 1.484 V VFB decreases 8
FB voltage where 2nd valley ends and 3rd valley starts VH3D 1.128 1.2 1.272 V VFB decreases 8
FB voltage where 3rd valley ends and 4th valley starts VH4D 0.846 0.9 0.954 V VFB decreases 8
FB voltage where 4th valley ends and VCO starts VHVCOD 0.732 0.8 0.828 V VFB decreases 8
FB voltage where VCO ends and 4th valley starts VHVCOI 1.316 1.4 1.484 V VFB increases 8
FB voltage where 4th valley ends and 3rd valley starts VH4I 1.504 1.6 1.696 V VFB increases 8
FB voltage where 3rd valley ends and 2nd valley starts VH3I 1.692 1.8 1.908 V VFB increases 8
FB voltage where 2nd valley ends and 1st valley starts VH2I 1.88 2 2.12 V VFB increases 8
Thermal Shutdown TSHDN 140 170 °C Device switching (FSW around 65 kHz) 8
Overload Timer tOVLD 75 85 95 ms VFB = 4 V, VCS > VILIM 8
Soft-start duration tSSTART 2.8 3.8 4.8 ms VFB = 4 V, VCS ramping up, measured from 1st DRV pulse to VCS(peak) = 90% of VILIM 8
Clamp series resistor RFault(clamp) 1.3 1.55 1.8 kΩ 8
Fault detection level for OVP VOVP 2.35 2.5 2.65 V VFault increasing 8
Delay before latch confirmation tlatch(delay) 22.5 30 37.5 ms 8
Brown-Out level VBO 0.744 0.8 0.856 V VFault decreasing 8
Sourced hysteresis current IBO 9 10 11 µA VFault > VBO, VFault = VBO + 0.2 V 8
Delay before entering and exiting Brown-out tBO(delay) 22.5 30 37.5 ms 8
Supply Voltage (VCC) continuous maximum VCC(MAX) -0.3 28 V Maximum Power Supply voltage, VCC pin, continuous voltage 6
Maximum current for VCC pin ICC(MAX) -30 30 mA 6
Maximum driver pin voltage, DRV pin, continuous voltage VDRV(MAX) -0.3 20 V 6
Maximum current for DRV pin IDRV(MAX) -1000 1000 mA 6
Maximum voltage on low power pins (except pins DRV and VCC) VMAX -0.3 10 V 6
Current range for low power pins (except pins ZCD, DRV and VCC) IMAX -10 10 mA 6
Maximum current for ZCD pin IZCD(MAX) -2 3 mA 6
Maximum Junction Temperature TJ(MAX) 150 °C 6
Operating Temperature Range -40 125 °C 6
Thermal Resistance Junction-to-Air RJA 120 °C/W 6

CAD (KiCad official)

  • Symbol: NCP1380CDR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncp1380cdr2g-etched.step / ncp1380cdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp1380cdr2g.step / ncp1380cdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (28 pp, sha256 60099c2945957903, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF