component
NCP1340B10DR2G
Public Made by Adomby adom
onsemi AC-DC Controllers & Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownNCP1340B10DR2G
onsemi · AC-DC Controllers & Regulators · SOIC-8
NCP1340B10DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Fault | input | Controller enters fault mode if the voltage on this pin is pulled above or below the fault thresholds, and a precise pull-up current source allows direct interface with an NTC thermistor. |
| 2 | FB | input | Feedback input for the QR flyback controller that allows direct connection to an optocoupler. |
| 3 | ZCD/OPP | input | A resistor divider from the auxiliary winding to this pin provides input to the demagnetization detection comparator and sets the OPP compensation level. |
| 4 | CS | input | Input to the cycle-by-cycle current limit comparator. |
| 5 | GND | power_in | Ground reference. |
| 6 | DRV | output | Drive pin of the circuit with -0.5/+0.8 A high-current capability, suitable for driving high gate charge power MOSFETs. |
| 7 | VCC | power_in | Positive supply of the IC that starts operating when VCC exceeds 17 V and turns off below 9 V (typical), with an operating range of 9 V to 28 V after start-up. |
| 8 | HV | input | Input for the high-voltage startup and brownout detection circuits, also containing line removal detection to safely discharge the X2 capacitors, rated -0.3 to 700 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High Voltage Startup Circuit Input Voltage | VHV(MAX) | -0.3 | 700 | V | 5 | ||
| High Voltage Startup Circuit Input Current | IHV(MAX) | 20 | mA | 5 | |||
| Supply Input Voltage | VCC(MAX) | -0.3 | 30 | V | 5 | ||
| Supply Input Current | ICC(MAX) | 30 | mA | 5 | |||
| Supply Input Voltage Slew Rate | dVCC/dt | 1 | V/s | 5 | |||
| Maximum Junction Temperature | TJ(MAX) | 150 | °C | 5 | |||
| Storage Temperature Range | TSTG | -60 | 150 | °C | 5 | ||
| Operating Junction Temperature | TJ | -40 | 125 | °C | 5 | ||
| Power Dissipation | PD(MAX) | 450 | mW | D Suffix, SOIC-8; TA = 25°C, 1 oz. Cu, 42 mm2 Copper Clad PCB | 5 | ||
| Thermal Resistance Junction-to-Ambient | RθJA | 225 | °C/W | D Suffix, SOIC-8; TA = 25°C, 1 oz. Cu, 42 mm2 Copper Clad PCB | 5 | ||
| Startup Threshold (Version B10) | VCC(on) | 14 | 15 | 16 | V | VCC increasing | 6 |
| Minimum Operating Voltage | VCC(off) | 8.5 | 9 | 9.5 | V | VCC decreasing | 6 |
| Operating Hysteresis (Version B10) | VCC(HYS) | 5.5 | V | VCC(on) − VCC(off) | 6 | ||
| Internal Latch / Logic Reset Level | VCC(reset) | 4.5 | 6.5 | 7.5 | V | VCC decreasing | 6 |
| Transition from Istart1 to Istart2 | VCC(inhibit) | 0.4 | 0.7 | 1.05 | V | VCC increasing, IHV = 650 µA | 6 |
| VCC(off) Delay | tdelay(VCC_off) | 25 | 32 | 40 | µs | VCC decreasing | 6 |
| Startup Delay | tdelay(start) | 500 | µs | Delay from VCC(on) to DRV Enable | 6 | ||
| Minimum Voltage for Start-Up Current Source | VHV(MIN) | 30 | V | 6 | |||
| Inhibit Current Sourced from VCC Pin | Istart1 | 0.2 | 0.5 | 0.65 | mA | Vcc = 0 V | 6 |
| Start-Up Current Sourced from VCC Pin | Istart2 | 2.4 | 3.75 | 5 | mA | Vcc = Vcc(on), 0.5 V, -40°C to 105°C | 6 |
| Start-Up Current Sourced from VCC Pin | Istart2 | 2 | 3.75 | 5 | mA | Vcc = Vcc(on), 0.5 V, -40°C to 125°C | 6 |
| Start-Up Circuit Off-State Leakage Current | IHV(off1) | 15 | µA | VHV = 162.5 V | 6 | ||
| Start-Up Circuit Off-State Leakage Current | IHV(off2) | 20 | µA | VHV = 325 V | 6 | ||
| Start-Up Circuit Off-State Leakage Current | IHV(off3) | 50 | µA | VHV = 700 V | 6 | ||
| Supply Current, Fault or Latch | ICC1 | 0.115 | 0.15 | mA | VCC = VCC(on), 0.5 V | 6 | |
| Supply Current, Skip Mode (excluding FB current) | ICC2 | 0.23 | 0.315 | mA | VFB = 0 V | 6 | |
| Supply Current, Operating | ICC3 | 1 | 1.5 | mA | fsw = 50 kHz, CDRV = open | 6 | |
| VCC Overvoltage Protection Threshold | VCC(OVP) | 27 | 28 | 29 | V | 6 | |
| VCC Overvoltage Protection Delay | tdelay(VCC_OVP) | 25 | 32 | 40 | µs | 6 | |
| Gate Drive Rise Time | tDRV(rise) | 20 | 40 | ns | VDRV from 10% to 90% | 6 | |
| Gate Drive Fall Time | tDRV(fall) | 5 | 30 | ns | VDRV from 90% to 10% | 6 | |
| Driver Source Current Capability | IDRV(SRC) | 500 | mA | 7 | |||
| Driver Sink Current Capability | IDRV(SNK) | 800 | mA | 7 | |||
| Driver High State Voltage | VDRV(high1) | 8 | V | VCC = VCC(off) + 0.2 V, RDRV = 10 kΩ | 7 | ||
| Driver High State Voltage | VDRV(high2) | 10 | 12 | 14 | V | VCC = 30 V, RDRV = 10 kΩ | 7 |
| Driver Low State Voltage | VDRV(low) | 0.25 | V | VFault = 0 V | 7 | ||
| FB Open Pin Voltage | VFB(open) | 4.8 | 5 | 5.1 | V | Versions B5/B6/A6 | 7 |
| FB Internal Pull-Up Resistor | RFB | 17 | 20 | 23 | kΩ | VFB = 0.4 V, Versions A6, B4-B10 | 7 |
| Valley Transition 1st to 2nd | V1to2 | 1.316 | 1.4 | 1.484 | V | VFB decreasing | 7 |
| Valley Transition 2nd to 3rd | V2to3 | 1.128 | 1.2 | 1.272 | V | VFB decreasing | 7 |
| Valley Transition 3rd to 4th | V3to4 | 1.034 | 1.1 | 1.166 | V | VFB decreasing | 7 |
| Valley Transition 4th to 5th | V4to5 | 0.94 | 1 | 1.06 | V | VFB decreasing | 7 |
| Valley Transition 5th to 6th | V5to6 | 0.846 | 0.9 | 0.954 | V | VFB decreasing | 7 |
| Valley Transition 6th to 5th | V6to5 | 1.41 | 1.5 | 1.59 | V | VFB increasing | 7 |
| Valley Transition 5th to 4th | V5to4 | 1.504 | 1.6 | 1.696 | V | VFB increasing | 7 |
| Valley Transition 4th to 3rd | V4to3 | 1.598 | 1.7 | 1.802 | V | VFB increasing | 7 |
| Valley Transition 3rd to 2nd | V3to2 | 1.692 | 1.8 | 1.908 | V | VFB increasing | 7 |
| Valley Transition 2nd to 1st | V2to1 | 1.88 | 2 | 2.12 | V | VFB increasing | 7 |
| Maximum On Time | ton(MAX) | 28 | 32 | 40 | µs | 7 | |
| ZCD threshold voltage | VZCD(trig) | 35 | 60 | 90 | mV | VZCD decreasing | 7 |
| ZCD hysteresis | VZCD(HYS) | 15 | 25 | 55 | mV | VZCD increasing | 7 |
| Demagnetization Propagation Delay | tdemag | 80 | 250 | ns | VZCD step from 4.0 V to −0.3 V | 7 | |
| ZCD Positive Clamp Voltage | VZCD(MAX) | 12.4 | 12.7 | 13 | V | IQZCD = 5.0 mA | 7 |
| ZCD Negative Clamp Voltage | VZCD(MIN) | -0.9 | -0.7 | 0 | V | IQZCD = −2.0 mA | 7 |
| ZCD Blanking Delay After Turn-Off | tZCD(blank) | 600 | 700 | 800 | ns | 7 | |
| Timeout After Last Demagnetization Detection | t(tout1) | 80 | 100 | 120 | µs | While in soft-start | 7 |
| Timeout After Last Demagnetization Detection | t(tout2) | 5.1 | 6 | 6.9 | µs | After soft-start complete | 7 |
| Current Limit Threshold Voltage | VILIM1 | 0.76 | 0.8 | 0.84 | V | VCS increasing | 7 |
| Leading Edge Blanking Duration | tLEB1 | 220 | 265 | 330 | ns | DRV minimum width minus tdelay(ILIM1) | 7 |
| Current Limit Threshold Propagation Delay | tdelay(ILIM1) | 95 | 175 | ns | Step VCS 0 V to VILIM1 + 0.5 V, VFB = 4 V | 8 | |
| PWM Comparator Propagation Delay | tdelay(PWM) | 125 | 175 | ns | Step VCS 0 V to 0.7 V, VFB = 2.4 | 8 | |
| Minimum Peak Current Freeze Setpoint | Vfreeze | 170 | 200 | 230 | mV | 8 | |
| Abnormal Overcurrent Fault Threshold | VILIM2 | 1.125 | 1.2 | 1.275 | V | VCS increasing, VFB = 4 V | 8 |
| Abnormal Overcurrent Fault Blanking Duration | tLEB2 | 80 | 110 | 140 | ns | DRV minimum width minus tdelay(ILIM2) | 8 |
| Abnormal Overcurrent Fault Propagation Delay | tdelay(ILIM2) | 80 | 175 | ns | Step VCS 0 V to VILIM2 + 0.5 V, VFB = 4 V | 8 | |
| Overpower Signal Blanking Delay | tOPP(blank) | 220 | 280 | 330 | ns | 8 | |
| Soft-Start Period | tSSTART | 2.8 | 4 | 5 | ms | Measured from 1st DRV pulse to VCS = VILIM1 | 8 |
| Flyback Overload Fault Timer | tOVLD | 120 | 160 | 200 | ms | VCS = VILIM1, Other Versions | 8 |
CAD (KiCad official)
- Symbol:
NCP1340B10DR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp1340b10dr2g-etched.step/ncp1340b10dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp1340b10dr2g.step/ncp1340b10dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (43 pp, sha256
ab80e1458de58ce2, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).