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NCP12700BDNR2G

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onsemi AC-DC Controllers And Regulators, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCP12700BDNR2G

onsemi · AC-DC Controllers And Regulators · MSOP-10

NCP12700BDNR2G from onsemi, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 UVLO input UVLO is the input to the Standby and UVLO comparators, where a resistor divider from VIN to ground sets the enable voltage, hysteresis comes from a 5 µA pull-down source, and an external pull-down can disable the controller.
2 FLT bidirectional FLT is the input to a window comparator with upper and lower fault thresholds, and it sources a precision current for an NTC to ground for over-temperature protection, with the upper threshold usable for output over-voltage sensing.
3 SS passive SS sets the soft-start ramp of the peak current limit using an internal 15 µA current source and an external capacitor to ground, with typical values of 10 nF to 100 nF.
4 RT passive RT sets the oscillator frequency and requires a resistor to ground placed close to the IC, with typical values of 10 kΩ to 100 kΩ.
5 COMP passive COMP provides the compensated error voltage for the PWM and skip comparators and has an internal 5 kΩ pull-up that can bias an opto-coupler transistor.
6 CS input CS is the current sense input for the PWM and current limit comparators, held low for 60 ns after DRV goes high to blank leading-edge spikes, and an external low-pass filter is recommended.
7 GND power_in GND is the controller ground.
8 DRV output DRV is a high-current output that drives the external MOSFET gate, with source capability of 1 A and sink capability of 2.8 A.
9 VCC power_in VCC provides bias to the controller and should have an external decoupling capacitor to ground in the range of 1 to 10 µF; supply voltage is 9 to 20 V recommended with a 30 V absolute maximum.
10 VIN power_in VIN is the input to the high-voltage startup regulator, which can source more than 15 mA to temporarily bias VCC during startup, with VIN limited to 120 V maximum for MSOP10.

Key specifications

Parameter Value
Manufacturer onsemi
Package MSOP-10
Category Power Management (PMIC)
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High Voltage Startup Voltage (MSOP10) VIN(MAX) 120 V 5
High Voltage Startup Current IIN(MAX) 50 mA 5
Supply Voltage VCC(MAX) -0.3 30 V 5
Supply Current ICC(MAX) 50 mA 5
DRV Current (Peak) IDRV(MAX) 3.25 A 5
FLT Current IFLT(MAX) 10 mA 5
Max Voltage on Signal Pins VSIG(MAX) -0.3 5.5 V 5
Max Current on Signal Pins ISIG(MAX) 10 mA 5
Maximum Junction Temperature TJMAX 150 °C 5
Storage Temperature Range TSTG -55 150 °C 5
VIN Voltage (MSOP10) VIN 9 100 V 5
Supply Voltage − All VCC 9 20 V 5
Operating Temperature Range TJ -40 125 °C 5
Regulated Voltage VCC(REG) 7.6 8 8.4 V VCC = Open, ICC = 5 mA 6
Current Source Capability IVIN(SRC) 15 mA VIN = 9 V, VCC = 7 V 6
Off-State Leakage Current (xDNR2G) IVIN(OFF) 100 µA VCC = Open, VIN = 120 V, VUVLO = 0 6
Minimum Operating Voltage VCC(off) 6.2 6.5 6.8 V VCC decreasing 6
Supply Current SHDN ICC(SHDN) 50 µA VUVLO = 0 V 6
Supply Current STBY ICC(STBY) 750 µA VUVLO = 0.7 V 6
Supply Current Enable ICC(EN) 4 mA CDRV = Open, VCOMP = 2 V 6
Supply Current Fault ICC(FLT) 500 µA VFLT = 0 V 6
Current Limit Comparator Threshold VCS(LIM) 465 495 525 mV 6
Propagation Delay From Current Sense Limit to DRV Low tCS(DLY) 75 ns Step VCS from 0, 0.6 V 6
Propagation Delay From Short Circuit Limit to DRV Low tSCP(DLY) 75 ns VCS = 0.75 V 6
CS Leading Edge Blanking (LEB) tLEB(CS) 75 100 125 ns 6
SCP Leading Edge Blanking tLEB(SCP) 45 60 75 ns 6
Overload Timer Duration tCS(OVLD) 24 30 36 ms VCS = 0.6 V 6
Applied Slope Compensation @ Current Limit Comparator VSLP(ILIM) 83 102 123 mV VCOMP = Open; Measured at D80% 6
PWM Propagation Delay to DRV Low tPWM(Dly) 75 ns VCOMP = 2 V, Step from CS 0- 0.4 V 6
COMP Open Pin Voltage VCOMP(open) 4 4.7 V VCOMP = Open 6
COMP Output Current ICOMP 0.84 1 1.2 mA VCOMP = 0 6
Maximum Duty Cycle DMAX 76 80 84 % VCOMP = Open 6
Applied Slope Compensation @ PWM Comparator VSLP(PWM) 77 98 117 mV VCOMP = 2 V; Measured at D80% 7
Soft−Start End Threshold VSS(end) 2.85 3 3.15 V 7
Soft−Start Current ISS 12 15 18 µA VSS = 3 V 7
Oscillator Frequency 1 FOSC1 185 200 215 kHz 7
Oscillator Frequency 2 FOSC2 95 100 105 kHz RT = 100 k 7
Oscillator Frequency 3 FOSC3 450 500 550 kHz RT = 20 k 7
Standby Threshold VSTBY(th) 0.35 0.5 0.65 V VUVLO increasing 7
Reset Threshold VRST(th) 0.3 0.45 0.6 V VUVLO decreasing 7
UVLO Threshold VUVLO(th) 765 800 830 mV VUVLO increasing 7
UVLO Hysteresis Current IUVLO(HYS) 4.5 5 5.5 µA 7
UVLO Detection Delay Filter tUVLO(DLY) 0.5 1 s VUVLO = VUVLO(th) − 20 mV 7
OPP Gain Gm(OPP) 135 150 165 µA/V 7
Maximum Current (Operating Point) ICS(OPP1) 180 200 220 µA VUVLO = 2.33 V 7
DRV Rise Time tDRV(rise) 6 10 15 ns VDRV = 1.2 V to 10.8 V 7
DRV Fall Time tDRV(fall) 2.5 4 10 ns VDRV = 10.8 V to 1.2 V 7
DRV Clamp Voltage VDRV(clamp) 10 12 14 V VCC = 20 V, RDRV = 10 k 7
Minimum DRV Voltage VDRV(MIN) 6 V VCC = VCC(OFF) + 100 mV, RDRV = 10 k 8
Fault Source Current IFLT 80 85 90 µA 8
OTP Fault Threshold VFLT(OTP) 0.47 0.5 0.53 V 8
OTP Detection Filter Delay tOTP(DLY) 10 20 30 µs 8
OTP Fault Recovery Threshold VFLT(REC) 0.846 0.9 0.954 V 8
OVP Fault Threshold VFLT(OVP) 2.8 3 3.2 V 8
OVP Detection Filter Delay tOVP(DLY) 3 5 7 µs 8
Fault Clamp Voltage VFLT(CLAMP) 1.13 1.35 1.57 V VFLT = Open 8
Auto−recovery Timer tAR 0.8 1 1.2 s 8
Thermal Shutdown TSHDN 150 165 180 °C 8
Thermal Resistance Junction−to−Air (MSOP10) RθJ−A 165 °C/W Note 2: per JEDEC JESD51.7, two 1 oz copper planes, board 80x80x1.6 mm 5
Junction−to−Top Thermal Characterization Parameter (MSOP10) J−C 10 °C/W 5

CAD (KiCad official)

  • Symbol: NCP12700BDNR2G
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ncp12700bdnr2g-etched.step / ncp12700bdnr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp12700bdnr2g.step / ncp12700bdnr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (21 pp, sha256 be4a90bcf4661bd5, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF