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NCP1252DRG
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HANSCHIP semiconductor AC-DC Controllers And Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCP1252DRG
HANSCHIP semiconductor · AC-DC Controllers And Regulators · SOP-8
NCP1252DRG from HANSCHIP semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback input with 6.0 V open-loop voltage, 1.5 mA short-circuit current, 3.5 kΩ internal pull-up, and burst-mode thresholds of 0.3 V (enter) and 0.33 V (exit). |
| 2 | BO | input | Brown-out input that monitors a fraction of the input voltage and keeps the controller off while below the 1.00 V typical VBO threshold (0.97 to 1.03 V), with hysteresis set by a 10 µA typical sink current and absolute maximum rating of -0.3 V to 5 V. |
| 3 | CS | input | Current sense input connected through a resistor to GND to set the primary peak current, with a 1 V typical current-limit threshold (0.92 to 1.08 V), 160 ns typical leading-edge blanking, and absolute maximum rating of -0.3 V to 5 V. |
| 4 | RI | input | Resistor-to-ground pin that programs the switching frequency, where 43 kΩ gives 100 kHz and 8.5 kΩ gives 425 to 550 kHz, with the device rated up to 500 kHz and absolute maximum rating of -0.3 V to 5 V. |
| 5 | GND | power_in | Ground reference for the controller. |
| 6 | GATE | output | Totem-pole gate driver output for the power MOSFET, with gate voltage clamped to 18 V typical to protect MOSFETs limited to about 25 V. |
| 7 | VDD | power_in | IC DC supply input with a recommended range of 10 V to 26 V and absolute maximum of 30 V, a 11.7 V typical start-up threshold, a 9.0 V typical switching-stop threshold, and 27.5 V typical overvoltage protection. |
| 8 | SS | passive | Soft-start pin where a capacitor to ground sets the soft-start duration, with 10 µA typical charge current, 4.0 V typical completion threshold, and the pin held grounded during the internal delay timer. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (absolute maximum) | VDD | 30 | V | 4 | |||
| VDD DC Clamp Current | IDD | 10 | mA | 4 | |||
| FB Input Voltage | VFB | -0.3 | 5 | V | 4 | ||
| BO Input Voltage | VBO | -0.3 | 5 | V | 4 | ||
| CS Input Voltage | VCS | -0.3 | 5 | V | 4 | ||
| RI Input Voltage | VRI | -0.3 | 5 | V | 4 | ||
| SS Input Voltage | VSS | -0.3 | 5 | V | 4 | ||
| Operating Junction Temperature | TJ | -20 | 150 | ℃ | 4 | ||
| Storage Temperature Range | TSTG | -55 | 160 | ℃ | 4 | ||
| Lead Temperature | TL | 245 | ℃ | Wave Soldering or IR,10Seconds | 4 | ||
| ESD Human Body Model | 2.5 | KV | JEDEC:JESD22-A114 | 4 | |||
| ESD Machine Model | 250 | V | JEDEC:JESD22-A115 | 4 | |||
| SOP-8 Thermal Resistance (Junction-to-Air) | RJA | 150 | ℃/W | 4 | |||
| DC Supply Voltage (recommended) | VDD | 10 | 26 | V | 5 | ||
| Operating Ambient Temperature | TA | -25 | 125 | ℃ | 5 | ||
| Startup Current | IDD_ST | 20 | 100 | uA | VDD=VDD_ON-0.01V | 5 | |
| Operation Current 1 | IDD_OP1 | 0.5 | 1.4 | 2.2 | mA | FOSC=100KHz | 5 |
| Operation Current 2 | IDD_OP2 | 2 | 2.7 | 3.5 | mA | FOSC=100KHz,CL=1nF | 5 |
| Threshold Voltage to Startup | VDD_ON | 11.2 | 11.7 | 12.2 | V | VDD Rising | 5 |
| Threshold Voltage to Stop Switching in Normal Mode | VDD_OFF | 8.3 | 9 | 9.7 | V | VDD Falling | 5 |
| Over voltage protection voltage | VDD_OVP | 26.5 | 27.5 | 28.5 | V | 5 | |
| Current Limiting Threshold Voltage | VTH_OC | 0.92 | 1 | 1.08 | V | 5 | |
| Over Current Detection and Control Delay | TD_OC | 70 | 150 | ns | 5 | ||
| Normal Oscillation Frequency | FOSC | 92 | 100 | 108 | KHz | 6 | |
| Normal Oscillation Frequency | FOSC | 425 | 500 | 550 | KHz | RI=8.5KΩ | 6 |
| Frequency jitter range | FJR | -5 | 5 | % | 6 | ||
| Gate Source resistance | RSRC | 20 | 30 | Ω | 6 | ||
| Gate Sink resistance | RSINK | 10 | 19 | Ω | 6 | ||
| Gate clamp voltage | VGate_Clamp | 15 | 18 | V | VDD=25V, CL=1000pF | 6 | |
| High-state voltage drop | VH_Drop | 50 | 500 | mV | VDD=VDD_OFF+0.1V CL=1000pF | 6 | |
| Soft start charge current | ISS | 8.8 | 10 | 11 | uA | Short SS pin to GND | 6 |
| Soft start completion voltage threshold | VSS | 3.5 | 4 | 4.5 | V | 6 | |
| Internal delay before starting the Soft start when VDD_ON is reached | TSS_Delay | 100 | 120 | 155 | ms | 6 | |
| Current sense fault voltage level triggering the timer | VCS_Fault | 0.9 | 1 | 1.1 | V | 6 | |
| Timer delay before latching a fault (overload or short circuit) | TFault | 10 | 15 | 20 | mS | CS Pin>VCS_Fault | 6 |
| Brown out voltage | VBO | 0.97 | 1 | 1.03 | V | 6 | |
| Internal current source generating the Brown out hysteresis | IBO | 8.6 | 10 | 11.2 | uA | 6 |
CAD (KiCad official)
- Symbol:
NCP1252DRG - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ncp1252drg-etched.step/ncp1252drg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp1252drg.step/ncp1252drg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HANSCHIP semiconductor datasheet (13 pp, sha256
984919519c79fa73, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).