NCP1252CDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	FB	input	Feedback input that connects directly to an optocoupler collector.
2	BO	input	Brown-out input that monitors the input voltage image to provide brown-out protection.
3	CS	input	Current sense input that monitors the primary current and allows selection of the ramp compensation amplitude.
4	RT	passive	Timing element pin where a resistor connected to ground fixes the switching frequency.
5	GND	power_in	The controller ground pin.
6	Drv	output	Driver output that connects to the MOSFET gate, with a maximum voltage of -0.3 V to VCC.
7	VCC	power_in	Supply input accepting 8 V up to 28 V continuous (30 V transient for 10 ms with IVcc < 20 mA), with a maximum injected current of 20 mA.
8	SSTART	passive	Soft-start pin where a capacitor connected to ground selects the soft-start duration; it is grounded during the delay timer.

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	SOIC-8
Category	Power Management ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Startup threshold, A/B/C versions	VCC(on)	9.4	10	10.6	V	VCC increasing, A, B, C versions	4
Minimum operating voltage	VCC(off)	8.4	9	9.6	V	VCC decreasing	4
Hysteresis VCC(on) to VCC(min)	VCC(HYS)	0.9	1		V	A, B and C versions	4
Internal IC consumption, DRV open	ICC2	0.5	1.4	2.2	mA	Fsw =100 kHz, DRV = open	4
Internal IC consumption, CDRV=1 nF	ICC3	2	2.7	3.5	mA	Fsw =100 kHz, CDRV = 1 nF	4
Current sense voltage threshold	VILIM	0.92	1	1.08	V		4
Propagation delay CS to gate off	tILIM		70	150	ns	From CS detected to gate turned off	4
Internal ramp compensation voltage level	Vramp	3.15	3.5	3.85	V	@ 25°C (Note 4)	4
Oscillator frequency	fOSC	92	100	108	kHz	RT = 43 k & DRV pin = 47 k	4
Oscillator frequency	fOSC	425	500	550	kHz	RT = 8.5 k & DRV pin = 47 k	4
Maximum operating frequency	fMAX	500			kHz	Note 3	4
Maximum duty-cycle, C version	DCmaxC	61	65	69	%		4
FB pin maximum current	IFB	1.5			mA	FB pin = GND	4
DRV source resistance	RSRC		10	30	Ω		4
DRV sink resistance	RSINK		6	19	Ω		4
Start-up current, controller disabled	ICC1			100	µA	VCC < VCC(on) & VCC increasing from zero	4
Clamping voltage	VCL		15	18	V	VCC = 25 V, RDRV = 47 k, CDRV = 1 nF	5
High-state voltage drop	VDRV(clamp)		50	500	mV	VCC = VCC(min) + 100 mV, RDRV = 47 k, CDRV = 1 nF	5
Skip cycle level	Vskip	0.2	0.3	0.4	V		5
Soft-start charge current	ISS	8.8	10	11	µA	SS pin = GND	5
Soft start completion voltage threshold	VSS	3.5	4	4.5	V		5
Internal delay before soft start	SSdelay	100	120	155	ms	When VCC(on) is reached, A, B and C versions only	5
Current sense fault voltage level	FCS	0.9	1	1.1	V	Triggering the timer	5
Fault timer delay, A/B/C/D versions	Tfault	10	15	20	ms	When CS pin > FCS	5
Brown-out voltage	VBO	0.974	1	1.026	V		5
Brown-out hysteresis current source	IBO	8.8	10	11.2	µA	-5°C ≤ TJ ≤ +125°C	5
Brown-out hysteresis current source	IBO	8.6	10	11.2	µA	-25°C ≤ TJ ≤ +125°C	5
Power supply voltage, transient	VCC			30	V	10 ms with IVcc < 20 mA	2
Power supply voltage, continuous	VCC			28	V	Vcc pin, continuous	2
Maximum current injected into pin 7	IVcc			20	mA		2
Maximum voltage on DRV pin	VDRV	-0.3			V	-0.3 to VCC	2
Maximum voltage on low power pins		-0.3		10	V	except pin 6, 7	2
Thermal resistance junction-to-air, SOIC8	RθJA		169		°C/W	SOIC8	2
Maximum junction temperature	TJ(MAX)			150	°C		2
Storage temperature range	TSTG	-60		150	°C		2
ESD capability, HBM	ESDHBM			1.8	kV	HBM model	2
ESD capability, MM	ESDMM			200	V	Machine Model	2

CAD (KiCad official)

Symbol: NCP1252CDR2G
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ncp1252cdr2g-etched.step / ncp1252cdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp1252cdr2g.step / ncp1252cdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (22 pp, sha256 38a2460f33874aaf, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

NCP1252CDR2G

Verified NCP1252CDR2G

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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