component
NCP12400CAHAB0DR2G
Public Made by Adomby adom
onsemi AC-DC Controllers & Regulators, SOIC-7. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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NCP12400CAHAB0DR2G
onsemi · AC-DC Controllers & Regulators · SOIC-7
NCP12400CAHAB0DR2G from onsemi, in a SOIC-7. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FAULT | input | Pull the pin up or down to stop the controller, and an internal current source allows direct connection of an NTC for over temperature detection. |
| 2 | FB | input | An optocoupler connected to ground controls the output regulation, and the part goes to the low consumption Off mode if the FB pin is pulled to GND. |
| 3 | CS | input | This input senses the primary current for current-mode operation, offers an overpower compensation adjustment, and implements overvoltage protection. |
| 4 | GND | power_in | The controller ground. |
| 5 | DRV | output | Drives the external MOSFET. |
| 6 | VCC | power_in | This supply pin accepts up to 28 Vdc with overvoltage detection and is connected to an external auxiliary voltage. |
| 8 | HV | input | Connects to the rectified ac line for start-up current source, self-supply, brown-out detection, X2 capacitor discharge and HV sensing, and it is not allowed to connect this pin to a dc voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-7 |
| Category | Power Management ICs |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum voltage on DRV pin | -0.3 | 20 | V | DC current self-limited if operated within the allowed range (Note 2) | 5 | ||
| DRV pin current (peak) | -1000 | 1000 | mA | Peak | 5 | ||
| Power supply voltage, VCC pin, continuous voltage | VCC | -0.3 | 36 | V | Continuous voltage | 5 | |
| VCC pin current (peak) | VCC | -30 | 30 | mA | Peak | 5 | |
| Maximum voltage on HV pin | -0.3 | 750 | V | DC current self-limited if operated within the allowed range | 5 | ||
| HV pin current | -20 | 20 | mA | 5 | |||
| Maximum voltage on low power pins (except pin 5, pin 6 and pin 8) | Vmax | -0.3 | 5.5 | V | DC current self-limited if operated within the allowed range (Note 2) | 5 | |
| Low power pins current (peak) | -10 | 10 | mA | Peak | 5 | ||
| Operating Junction Temperature | TJMAX | -40 | 150 | °C | 5 | ||
| Storage Temperature Range | TSTRGMAX | -60 | 150 | °C | 5 | ||
| ESD Capability, HBM model (All pins except HV) | 4000 | V | HBM, all pins except HV (Note 1) | 5 | |||
| ESD Capability, HBM model (pin 8, HV) | 2000 | V | HBM, pin 8 (HV) | 5 | |||
| ESD Capability, Charge Discharge Model | 500 | V | Charge discharge model (Note 1) | 5 | |||
| Minimum voltage for current source operation | VHV(min) | 30 | 40 | V | 5 | ||
| Current flowing out of VCC pin | Istart1 | 0.2 | 0.5 | 0.8 | mA | VCC = 0 V | 5 |
| Current flowing out of VCC pin | Istart2 | 5 | 8 | 11 | mA | VCC = VCC(on) − 0.5 V | 5 |
| Off-state leakage current | Istart(off) | 2 | 6 | A | VHV = 750 V, VCC = 15 V | 5 | |
| HV current source restart threshold | VCC(min) | 9.5 | 10.5 | 11.5 | V | 5 | |
| Turn-off threshold | VCC(off) | 8.4 | 8.9 | 9.3 | V | 5 | |
| Overvoltage threshold | VCC(ovp) | 25 | 26.5 | 28 | V | Standard version (not option EAHBB, BBBBB) | 5 |
| VCC decreasing level at which the internal logic resets | VCC(reset) | 4.8 | 7 | 7.7 | V | 6 | |
| VCC level for ISTART1 to ISTART2 transition | VCC(inhibit) | 1 | 2.1 | 3 | V | 6 | |
| Internal current consumption | ICC1 | 1 | 1.3 | 2 | mA | DRV open, VFB = 3 V, 65 kHz | 6 |
| Internal current consumption | ICC3 | 1.5 | 2.1 | 2.9 | mA | Cdrv = 1 nF, VFB = 3 V, 65 kHz | 6 |
| Brown-out threshold (option C), VHV going up | VHV(start) | 87 | 95 | 103 | V | VHV going up | 6 |
| Brown-out threshold (option C), VHV going down | VHV(stop) | 85 | 93 | 101 | V | VHV going down | 6 |
| Comparator hysteresis observed at HV pin | VHV(hyst) | 2 | 3 | 4 | V | 6 | |
| Shunt regulator voltage at VCC pin during X2 discharge event | VCC(dis) | 10 | 11 | 12 | V | 6 | |
| Timer duration for no line detection | tDET | 21 | 32 | 43 | ms | 6 | |
| Discharge timer duration | tDIS | 21 | 32 | 43 | ms | 6 | |
| Oscillator frequency 65 kHz version | fOSC | 61 | 65 | 69 | kHz | 65 kHz version | 6 |
| Maximum duty-ratio (corresponding to maximum on time at maximum switching frequency) | DMAX | 75 | 80 | 85 | % | 6 | |
| Frequency jittering amplitude, in percentage of FOSC | Ajitter | 3 | 4 | 5 | kHz | Printed as ±3.0/±4.0/±5.0 kHz, percentage of FOSC | 6 |
| Frequency jittering modulation frequency | Fjitter | 85 | 125 | 165 | Hz | 6 | |
| Feedback voltage threshold below which frequency foldback starts | VFB(foldS) | 2.4 | 2.5 | 2.6 | V | TJ = 25°C | 6 |
| Feedback voltage threshold below which frequency foldback is complete | VFB(foldE) | 2.05 | 2.15 | 2.25 | V | TJ = 25°C | 6 |
| Minimum switching frequency | fOSC(min) | 25 | 28 | 31 | kHz | VFB = Vskip(in) + 0.1 | 6 |
| Rise time, 10 to 90% of VCC | trise | 40 | 70 | ns | VCC = VCC(off) + 0.2 V, CDRV = 1 nF | 7 | |
| Fall time, 90 to 10% of VCC | tfall | 30 | 60 | ns | VCC = VCC(off) + 0.2 V, CDRV = 1 nF | 7 | |
| Clamping voltage (maximum gate voltage) | VDRV(clamp) | 10 | 12 | 14 | V | VCC = VCC(ovp), 0.2 V, DRV high, RDRV = 33 k, Cload = 220 pF | 7 |
| High-state voltage drop | VDRV(drop) | 1 | V | VCC = VCC(min) + 0.2 V, RDRV = 33 k, DRV high | 7 | ||
| Maximum internal current setpoint | VILIM | 0.66 | 0.7 | 0.74 | V | VFB > 3.5 V | 7 |
| Propagation delay from VIlimit detection to DRV off | tdelay | 50 | 70 | ns | VCS = VILIM | 7 | |
| Leading Edge Blanking Duration for VILIM | tLEB | 180 | 250 | 320 | ns | 7 | |
| Threshold for immediate fault protection activation | VCS(stop) | 0.95 | 1.05 | 1.15 | V | 7 | |
| Leading Edge Blanking Duration for VCS(stop) | tBCS | 75 | 120 | 150 | ns | Note 6 | 7 |
| Soft-start duration (option A) | tSSTART | 3.2 | 4 | 4.8 | ms | From 1st pulse to VCS = VILIM | 7 |
| Frozen current setpoint (option H) | VI(freeze) | 250 | 300 | 350 | mV | Option H | 7 |
| Over voltage protection threshold when DRV is low | VOVP(CS) | 1 | 1.05 | 1.1 | V | VCS going up | 7 |
| Blanking duration on OVP detection | tOVP,CS | 0.7 | 1 | 1.3 | s | 7 | |
| Internal pull-up resistor | RFB(up) | 30 | 40 | 50 | k | TJ = 25°C | 7 |
| Feedback voltage thresholds for skip mode, VFB going down | Vskip(in) | 0.9 | 1 | 1.1 | V | VFB going down, TJ = 25°C | 7 |
| Feedback voltage thresholds for skip mode, VFB going up | Vskip(out) | 1.05 | 1.15 | 1.25 | V | VFB going up, TJ = 25°C | 7 |
| Internal pull-up voltage on the FB pin | VFB(ref) | 4.5 | 5 | 5.5 | V | 7 | |
| The voltage below which the part enters the off mode | VOFF | 0.5 | 0.6 | 0.7 | V | VCC > VCC(off) | 8 |
| Fault timer duration | tfault | 108 | 128 | 178 | ms | 8 | |
| Fault timer reset time | tfault,res | 150 | 200 | 250 | s | VCS < 0.7 V, D < 90% DMAX | 8 |
| Autorecovery mode latch-off time duration | tautorec | 0.85 | 1 | 1.35 | s | 8 | |
| FB voltage above which IOPC is applied | VFB(OPCF) | 2.6 | V | VHV = 365 V | 8 | ||
| High threshold | VOVP | 2.43 | 2.5 | 2.57 | V | VLatch going up | 8 |
| Low threshold | VOTP | 0.38 | 0.4 | 0.42 | V | VLatch going down, TJ = 25°C | 8 |
| OTP resistance threshold (TJ = 25°C) | ROTP | 7.6 | 8 | 8.5 | k | External NTC resistance is going down | 8 |
| Temperature shutdown | TTSD | 150 | °C | TJ going up | 8 | ||
| Temperature shutdown hysteresis | TTSD(HYS) | 30 | °C | TJ going down | 8 | ||
| Thermal Resistance Junction-to-Air, low conductivity PCB | RJ-A | 162 | °C/W | SOIC-7, low conductivity PCB (Note 3) | 5 | ||
| Thermal Resistance Junction-to-Case | RJ-C | 73 | °C/W | SOIC-7 | 5 |
CAD (KiCad official)
- Symbol:
NCP12400CAHAB0DR2G - Footprint:
Package_SO:SOIC-8-N7_3.9x4.9mm_P1.27mm - 3D model: SOIC-7 (KiCad packages3D, STEP)
- 3D model files:
ncp12400cahab0dr2g-etched.step/ncp12400cahab0dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp12400cahab0dr2g.step/ncp12400cahab0dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (47 pp, sha256
5b6a98e6b6537aad, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).