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NCP1230D65R2G

Public Made by Adom

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onsemi AC-DC Controllers & Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsncp1230d65r2gfactory-2.0.0extractor-text
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Contents

README

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NCP1230D65R2G

onsemi · AC-DC Controllers & Regulators · SOIC-8

NCP1230D65R2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PFC VCC power_out Provides bias voltage to the PFC controller via a low-impedance switch to the VCC pin (Pin 6); the switch is open in standby, startup and fault conditions and closes once the aux. winding is stabilized.
2 FB input Feedback input pulled low by an optocoupler collector to regulate; when the current setpoint reaches 25% of maximum peak the controller skips cycles (max 10 V).
3 CS/OVP input Current sense input with internal ramp compensation and a 3.0 V latch-off level that latches the output off until VCC is recycled (max 10 V).
4 GND power_in IC ground.
5 DRV output Driver output with +500 mA/-800 mA drive capability for large Qg MOSFETs (max 18 V, 1.0 A).
6 VCC power_in Supply input accepting voltages up to 18 V with a typical UVLO turn-off threshold of 7.7 V.
7 NC unconnected No connection.
8 HV power_in High-voltage startup input connected to the bulk voltage for lossless startup, rated to 500 V maximum.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Turn-On Threshold Level, VCC Going Up VCCOFF 11.6 12.6 13.6 V Vfb = 2.0 V 5
Minimum Operating Voltage after Turn-On VCC(min) 7 7.7 8.4 V 5
VCC Decreasing Level at which Latch-Off Phase Ends VCClatch 5 5.6 6.2 V Vfb = 3.5 V 5
Internal IC Consumption, No Output Load ICC1 0.6 1.1 1.8 mA Vfb = 2.5 V 5
Internal IC Consumption, 1.0 nF Load, FSW = 65 kHz ICC2 1.3 1.8 2.5 mA Vfb = 2.5 V 5
Internal IC Consumption, Latch-Off Phase ICC3 400 680 1000 µA 5
High-Voltage Current Source, 1.0 nF Load IC1 1.8 3.2 4.2 mA VCCOFF -0.2 V, Vfb = 2.5 V, VPIN8 = 30 V 5
High-Voltage Current Source IC2 1.8 4.4 5.6 mA VCC = 0 V 5
Minimum Startup Voltage VHVmin 20 23 V Ic = 0.5 mA, VCCOFF -0.2 V, Vfb = 2.5 V 5
Startup Leakage IHVLeak 10 30 80 µA VPIN8 = 500 V 5
Source Resistance ROH 6 12.3 25 Ω RLoad 300 Ω, Vfb = 2.5 V 5
Sink Resistance ROL 3 7.5 18 Ω 1.0 V on Pin 5, Vfb = 3.5 V 5
Pin 1 Output Impedance RPFC 6 11.7 23 Ω Rload on Pin 1 = 680 Ω 5
Maximum Internal Current Setpoint ILimit 1.01 1.063 1.116 V Tj = 25°C 5
Maximum Internal Current Setpoint ILimit 0.979 1.127 V Tj = -40°C to +125°C 5
Default Internal Setpoint for Skip Cycle and Standby Detection Vskip 600 750 900 mV 5
Default Internal Setpoint to Leave Standby Vstby-out 1 1.25 1.5 V 5
Propagation Delay from CS Detected to Gate Turned Off TDEL CS 90 180 ns VGate = 10 V, Pin 5 loaded by 1.0 nF 5
Leading Edge Blanking Duration TLEB 100 200 350 ns 5
Temperature Shutdown, Maximum Value TSD 150 165 °C Verified by design 5
Oscillation Frequency, 65 kHz Version fOSC 60 65 70 kHz Tj = 25°C, Vfb = 2.5 V 6
Oscillation Frequency, 65 kHz Version fOSC 58 72 kHz Tj = 0°C to +125°C 6
Oscillation Frequency, 65 kHz Version fOSC 55 72 kHz Tj = -40°C to +125°C 6
Maximum Duty-Cycle Dmax 75 80 85 % CS = 0, Vfb = 2.5 V 6
Internal Resistor (Ramp Compensation) Rup 9 18 36 kΩ Verified by design 6
Opto Current Source 200 235 270 µA Vfb = 0.75 V 6
Latch-Off Level Vlatch 2.7 3 3.3 V 6
VCC Level at which Internal Logic gets Reset VCCreset 4 V 5
Output Voltage Rise-Time Tr 40 ns CL = 1.0 nF, 10-90% 5
Output Voltage Fall-Time Tf 15 ns CL = 1.0 nF, 10-90% 5
Soft-Start Period SS 2.5 ms Verified by design 5
Hysteresis in Temperature Shutdown TSD hyste 25 °C Verified by design 5
Maximum Voltage on Pin 8 VDS -0.3 500 V 4
Power Supply Voltage, Pin 6 VCC -0.3 18 V 4
Drive Output Voltage, Pin 5 VDV 18 V 4
Drive Current Io 1 A 4
Voltage Current Sense Pin, Pin 3 Vcs 10 V 4
Voltage Feedback, Pin 2 Vfb 10 V 4
Voltage, Pin 1 VPFC 18 V 4
Maximum Continuous Current from Pin 1 IPFC 35 mA 4
Maximum Power Dissipation SOIC Pmax 0.702 W TA = 25°C 4
Maximum Junction Temperature TJ 150 °C 4
Storage Temperature Range Tstg -60 150 °C 4
Thermal Resistance, Junction-to-Air, SOIC Version RθJA 178 °C/W 4

CAD (KiCad official)

  • Symbol: NCP1230D65R2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncp1230d65r2g-etched.step / ncp1230d65r2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp1230d65r2g.step / ncp1230d65r2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (21 pp, sha256 dfa5f53a68c96ece, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF