component
NCP1031DR2G
Public Made by Adomby adom
onsemi AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NCP1031DR2G
onsemi · AC-DC Controllers And Regulators · SOIC-8
NCP1031DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin for the circuit. |
| 2 | CT | passive | An external capacitor connected to this pin sets the oscillator frequency up to 1 MHz, and the frequency is reduced by a factor of 7 when a fault condition exists. |
| 3 | VFB | input | The regulated output voltage is scaled down to 2.5 V by a resistor divider and compared to an internal 2.5 V reference. |
| 4 | COMP | passive | Requires an external compensation network between COMP and VFB, and is effectively grounded when faults are present. |
| 5 | OV | input | Line voltage is scaled down by an external resistor divider so that OV reaches 2.5 V at the maximum operating line voltage. |
| 6 | UV | input | Line voltage is scaled down by an external resistor divider so that UV reaches 2.5 V at the minimum operating line voltage. |
| 7 | VCC | power_in | Connected to an external energy storage capacitor; the startup circuit charges it at turn-on and VCC should not exceed 16 V. |
| 8 | VDRAIN | passive | Connects the power switch and startup circuits directly to one transformer winding; VDRAIN should not exceed 200 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Switch and Startup Circuits Voltage | VDRAIN | -0.3 | 200 | V | 4 | ||
| Power Switch and Startup Circuits Input Current (NCP1031) | IDRAIN | 2 | A | 4 | |||
| VCC Voltage Range | VCC | -0.3 | 16 | V | 4 | ||
| All Other Inputs/Outputs Voltage Range | VIO | -0.3 | 10 | V | 4 | ||
| VCC and All Other Inputs/Outputs Current | IIO | 100 | mA | 4 | |||
| Operating Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage Temperature | Tstg | -55 | 150 | °C | 4 | ||
| Power Dissipation, D Suffix Plastic Package Case 751 (SOIC-8) | 0.893 | W | TJ = 25°C, 2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad | 4 | |||
| Thermal Resistance, Junction to Air, D Suffix Case 751 | RJA | 112 | °C/W | 2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad | 4 | ||
| ESD Human Body Model, pins 1-7 | 2000 | V | Pins 1-7, per MIL-STD-883 Method 3015 | 4 | |||
| ESD Machine Model, pins 1-7 | 200 | V | Pins 1-7, Machine Model Method | 4 | |||
| Startup Threshold Voltage (VCC Increasing) | VCC(on) | 9.6 | 10.2 | 10.6 | V | VFB = 2.7 V | 5 |
| Minimum Operating VCC After Turn-on (VCC Decreasing) | VCC(off) | 7 | 7.6 | 8 | V | VFB = 2.7 V | 5 |
| Undervoltage Lockout Threshold Voltage, VCC Decreasing | VCC(reset) | 6 | 6.6 | 7 | V | VFB = VCOMP | 5 |
| Minimum Startup Voltage (Pin 8) | VSTART(min) | 16.8 | 18.5 | V | ISTART = 0.5 mA, VCC = VCC(on) − 0.2 V | 5 | |
| Reference Voltage (Follower Mode) | VREF | 2.45 | 2.5 | 2.55 | V | VCOMP = VFB, TJ = 25°C | 5 |
| Reference Voltage (Follower Mode) | VREF | 2.4 | 2.5 | 2.6 | V | VCOMP = VFB, TJ = −40°C to 125°C | 5 |
| Line Regulation | REGLINE | 1 | 5 | mV | VCC = 8 V to 16 V, TJ = 25°C | 5 | |
| Input Bias Current | IVFB | 0.1 | 1 | µA | VFB = 2.3 V | 5 | |
| COMP Source Current | ISRC | 80 | 110 | 140 | µA | 5 | |
| COMP Sink Current | ISNK | 200 | 550 | 900 | µA | VFB = 2.7 V | 5 |
| COMP Maximum Voltage | VC(max) | 4.5 | V | ISRC = 0 A | 5 | ||
| COMP Minimum Voltage | VC(min) | 1 | V | ISNK = 0 A, VFB = 2.7 V | 5 | ||
| Undervoltage Lockout Voltage Threshold (Vin Increasing) | VUV | 2.4 | 2.55 | 2.7 | V | VFB = VCOMP | 5 |
| Undervoltage Voltage Hysteresis | VUV(hys) | 0.075 | 0.175 | 0.275 | V | VFB = VCOMP | 5 |
| Undervoltage Input Bias Current | IUV | 0 | 1 | µA | VFB = VCOMP | 5 | |
| Overvoltage Lockout Voltage Threshold (Vin Increasing) | VOV | 2.4 | 2.55 | 2.7 | V | VFB = VCOMP | 5 |
| Overvoltage Voltage Hysteresis | VOV(hys) | 0.075 | 0.175 | 0.275 | V | VFB = VCOMP | 5 |
| Overvoltage Input Bias Current | IOV | 0 | 1 | µA | VFB = VCOMP | 5 | |
| Oscillator Frequency | fOSC1 | 275 | 300 | kHz | CT = 560 pF, TJ = 25°C | 6 | |
| Oscillator Frequency | fOSC1 | 260 | 325 | kHz | CT = 560 pF, TJ = −40°C to 125°C | 6 | |
| Oscillator Ramp Valley | Vrvly | 3 | V | 6 | |||
| Oscillator Ramp Peak | Vrpk | 3.5 | V | 6 | |||
| Maximum Duty Cycle | DCMAX | 70 | 75 | 80 | % | 6 | |
| Power Switch Circuit On-State Resistance (NCP1031) | RDS(on) | 2.1 | 3 | Ω | ID = 100 mA, TJ = 25°C | 6 | |
| Power Switch Circuit On-State Resistance (NCP1031) | RDS(on) | 3.5 | 6 | Ω | ID = 100 mA, TJ = 125°C | 6 | |
| Power Switch and Startup Circuit Breakdown Voltage | V(BR)DS | 200 | V | ID = 100 µA, TJ = 25°C | 6 | ||
| Power Switch and Startup Circuit Off-State Leakage Current | IDS(off) | 50 | µA | VDRAIN = 200 V, VUV = 2.0 V, TJ = −40 to 125°C | 6 | ||
| Current Limit Threshold (NCP1031) | ILIM | 700 | 1050 | 1360 | mA | TJ = 25°C, di/dt = 1.0 A/µs | 6 |
| Supply Current After UV Turn-On, Power Switch Enabled | ICC1 | 2 | 3 | 4 | mA | Non-fault condition (VFB = 2.7 V) | 6 |
| Supply Current After UV Turn-On, Power Switch Disabled | ICC2 | 1.5 | 2 | mA | Power Switch Disabled | 6 | |
| Supply Current After UV Turn-On, Fault Condition | ICC3 | 0.65 | 1.2 | mA | Fault Condition (VFB = 2.7 V, VUV = 2.0 V) | 6 |
CAD (KiCad official)
- Symbol:
NCP1031DR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp1031dr2g-etched.step/ncp1031dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp1031dr2g.step/ncp1031dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (21 pp, sha256
9d1c98817b6525b0, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NCP1031DR2G
**onsemi** · AC-DC Controllers And Regulators · SOIC-8
NCP1031DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin for the circuit. |
| 2 | CT | passive | An external capacitor connected to this pin sets the oscillator frequency up to 1 MHz, and the frequency is reduced by a factor of 7 when a fault condition exists. |
| 3 | VFB | input | The regulated output voltage is scaled down to 2.5 V by a resistor divider and compared to an internal 2.5 V reference. |
| 4 | COMP | passive | Requires an external compensation network between COMP and VFB, and is effectively grounded when faults are present. |
| 5 | OV | input | Line voltage is scaled down by an external resistor divider so that OV reaches 2.5 V at the maximum operating line voltage. |
| 6 | UV | input | Line voltage is scaled down by an external resistor divider so that UV reaches 2.5 V at the minimum operating line voltage. |
| 7 | VCC | power_in | Connected to an external energy storage capacitor; the startup circuit charges it at turn-on and VCC should not exceed 16 V. |
| 8 | VDRAIN | passive | Connects the power switch and startup circuits directly to one transformer winding; VDRAIN should not exceed 200 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Switch and Startup Circuits Voltage | VDRAIN | -0.3 | | 200 | V | | 4 |
| Power Switch and Startup Circuits Input Current (NCP1031) | IDRAIN | | | 2 | A | | 4 |
| VCC Voltage Range | VCC | -0.3 | | 16 | V | | 4 |
| All Other Inputs/Outputs Voltage Range | VIO | -0.3 | | 10 | V | | 4 |
| VCC and All Other Inputs/Outputs Current | IIO | | | 100 | mA | | 4 |
| Operating Junction Temperature | TJ | -40 | | 150 | °C | | 4 |
| Storage Temperature | Tstg | -55 | | 150 | °C | | 4 |
| Power Dissipation, D Suffix Plastic Package Case 751 (SOIC-8) | | | | 0.893 | W | TJ = 25°C, 2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad | 4 |
| Thermal Resistance, Junction to Air, D Suffix Case 751 | RJA | | 112 | | °C/W | 2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad | 4 |
| ESD Human Body Model, pins 1-7 | | | | 2000 | V | Pins 1-7, per MIL-STD-883 Method 3015 | 4 |
| ESD Machine Model, pins 1-7 | | | | 200 | V | Pins 1-7, Machine Model Method | 4 |
| Startup Threshold Voltage (VCC Increasing) | VCC(on) | 9.6 | 10.2 | 10.6 | V | VFB = 2.7 V | 5 |
| Minimum Operating VCC After Turn-on (VCC Decreasing) | VCC(off) | 7 | 7.6 | 8 | V | VFB = 2.7 V | 5 |
| Undervoltage Lockout Threshold Voltage, VCC Decreasing | VCC(reset) | 6 | 6.6 | 7 | V | VFB = VCOMP | 5 |
| Minimum Startup Voltage (Pin 8) | VSTART(min) | | 16.8 | 18.5 | V | ISTART = 0.5 mA, VCC = VCC(on) − 0.2 V | 5 |
| Reference Voltage (Follower Mode) | VREF | 2.45 | 2.5 | 2.55 | V | VCOMP = VFB, TJ = 25°C | 5 |
| Reference Voltage (Follower Mode) | VREF | 2.4 | 2.5 | 2.6 | V | VCOMP = VFB, TJ = −40°C to 125°C | 5 |
| Line Regulation | REGLINE | | 1 | 5 | mV | VCC = 8 V to 16 V, TJ = 25°C | 5 |
| Input Bias Current | IVFB | | 0.1 | 1 | µA | VFB = 2.3 V | 5 |
| COMP Source Current | ISRC | 80 | 110 | 140 | µA | | 5 |
| COMP Sink Current | ISNK | 200 | 550 | 900 | µA | VFB = 2.7 V | 5 |
| COMP Maximum Voltage | VC(max) | 4.5 | | | V | ISRC = 0 A | 5 |
| COMP Minimum Voltage | VC(min) | | | 1 | V | ISNK = 0 A, VFB = 2.7 V | 5 |
| Undervoltage Lockout Voltage Threshold (Vin Increasing) | VUV | 2.4 | 2.55 | 2.7 | V | VFB = VCOMP | 5 |
| Undervoltage Voltage Hysteresis | VUV(hys) | 0.075 | 0.175 | 0.275 | V | VFB = VCOMP | 5 |
| Undervoltage Input Bias Current | IUV | | 0 | 1 | µA | VFB = VCOMP | 5 |
| Overvoltage Lockout Voltage Threshold (Vin Increasing) | VOV | 2.4 | 2.55 | 2.7 | V | VFB = VCOMP | 5 |
| Overvoltage Voltage Hysteresis | VOV(hys) | 0.075 | 0.175 | 0.275 | V | VFB = VCOMP | 5 |
| Overvoltage Input Bias Current | IOV | | 0 | 1 | µA | VFB = VCOMP | 5 |
| Oscillator Frequency | fOSC1 | 275 | | 300 | kHz | CT = 560 pF, TJ = 25°C | 6 |
| Oscillator Frequency | fOSC1 | 260 | | 325 | kHz | CT = 560 pF, TJ = −40°C to 125°C | 6 |
| Oscillator Ramp Valley | Vrvly | 3 | | | V | | 6 |
| Oscillator Ramp Peak | Vrpk | | | 3.5 | V | | 6 |
| Maximum Duty Cycle | DCMAX | 70 | 75 | 80 | % | | 6 |
| Power Switch Circuit On-State Resistance (NCP1031) | RDS(on) | | 2.1 | 3 | Ω | ID = 100 mA, TJ = 25°C | 6 |
| Power Switch Circuit On-State Resistance (NCP1031) | RDS(on) | | 3.5 | 6 | Ω | ID = 100 mA, TJ = 125°C | 6 |
| Power Switch and Startup Circuit Breakdown Voltage | V(BR)DS | 200 | | | V | ID = 100 µA, TJ = 25°C | 6 |
| Power Switch and Startup Circuit Off-State Leakage Current | IDS(off) | | | 50 | µA | VDRAIN = 200 V, VUV = 2.0 V, TJ = −40 to 125°C | 6 |
| Current Limit Threshold (NCP1031) | ILIM | 700 | 1050 | 1360 | mA | TJ = 25°C, di/dt = 1.0 A/µs | 6 |
| Supply Current After UV Turn-On, Power Switch Enabled | ICC1 | 2 | 3 | 4 | mA | Non-fault condition (VFB = 2.7 V) | 6 |
| Supply Current After UV Turn-On, Power Switch Disabled | ICC2 | | 1.5 | 2 | mA | Power Switch Disabled | 6 |
| Supply Current After UV Turn-On, Fault Condition | ICC3 | | 0.65 | 1.2 | mA | Fault Condition (VFB = 2.7 V, VUV = 2.0 V) | 6 |
## CAD (KiCad official)
- Symbol: `NCP1031DR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ncp1031dr2g-etched.step` / `ncp1031dr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp1031dr2g.step` / `ncp1031dr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588879860249350144) (21 pp, sha256 `9d1c98817b6525b0`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ncp1031dr2g-datasheet.pdf)