component
NCN8025MTTBG
Public Made by Adomby adom
onsemi Interface - Specialized, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NCN8025MTTBG
onsemi · Interface - Specialized · QFN-16-EP(3x3)
NCN8025MTTBG from onsemi, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSEL0 | input | Selects card VCC mode: VSEL0 Low gives 5 V (VSEL1 High) or 3 V (VSEL1 Low); VSEL0 High gives 1.8 V (VSEL1 High) or 3 V (VSEL1 Low). |
| 2 | VDDP | power_in | Regulator power supply (LDO input), 2.7 V to 5.5 V depending on CVCC mode, with 10 µF + 100 nF decoupling close to the pin. |
| 3 | PRES | input | Card presence input, active (card present) when Low, with a built-in debounce timer of about 8 ms, for Normally Open smart card connectors. |
| 4 | CI/O | bidirectional | Card serial I/O (C7) connection with a bidirectional level translator to the microcontroller and a typical 11 kΩ pull-up to CVCC. |
| 5 | CCLK | output | Clock output to the card connector (C3), derived from CLKIN through the clock dividers and level shifter. |
| 6 | CRST | output | Reset output to the card (C2), level-shifted from RSTIN according to the programmed CVCC value. |
| 7 | CVCC | power_out | Card power supply output (C1) from the internal LDO programmable to 1.8 V, 3 V or 5 V, sourcing up to 70 mA and requiring 80 nF to 1.2 µF low-ESR (<100 mΩ) ceramic capacitance. |
| 8 | CMDVCC | input | Active-Low command VCC input; the activation sequence starts when CMDVCC toggles High to Low with a card present. |
| 9 | RSTIN | input | Reset input from the host referred to VDD, level-shifted to the card reset pin according to the programmed CVCC. |
| 10 | VDD | power_in | Controller-side supply, 2.7 V to 5.5 V, with a 0.1 µF decoupling capacitor; card pins are disabled when VDD falls below 2.30 V typical. |
| 11 | INT | output | Active-Low interrupt output that signals card presence and faults such as CVCC overload. |
| 12 | CLKIN | input | External clock input, up to 27 MHz. |
| 13 | I/Ouc | bidirectional | Microcontroller-side serial I/O with a bidirectional level translator to the card and a built-in constant 11 kΩ typical pull-up. |
| 14 | CLKDIV1 | input | Clock division ratio programming input, used together with CLKDIV2 (ratios 1, 1/2, 1/4, 1/8). |
| 15 | CLKDIV2 | input | Clock division ratio programming input, used together with CLKDIV1 (ratios 1, 1/2, 1/4, 1/8). |
| 16 | VSEL1 | input | Card VCC voltage select input: with VSEL0 Low, High gives 5 V and Low gives 3 V; with VSEL0 High, High gives 1.8 V and Low gives 3 V. |
| 17 | GND | power_in | Regulator power supply ground, connected to the exposed pad, which must be connected to the PCB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | QFN-16-EP(3x3) |
| Category | Interface ICs |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
NCN8025MTTBG - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ncn8025mttbg-etched.step/ncn8025mttbg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncn8025mttbg.step/ncn8025mttbg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (15 pp, sha256
c26d5c0564f47926, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NCN8025MTTBG
**onsemi** · Interface - Specialized · QFN-16-EP(3x3)
NCN8025MTTBG from onsemi, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSEL0 | input | Selects card VCC mode: VSEL0 Low gives 5 V (VSEL1 High) or 3 V (VSEL1 Low); VSEL0 High gives 1.8 V (VSEL1 High) or 3 V (VSEL1 Low). |
| 2 | VDDP | power_in | Regulator power supply (LDO input), 2.7 V to 5.5 V depending on CVCC mode, with 10 µF + 100 nF decoupling close to the pin. |
| 3 | PRES | input | Card presence input, active (card present) when Low, with a built-in debounce timer of about 8 ms, for Normally Open smart card connectors. |
| 4 | CI/O | bidirectional | Card serial I/O (C7) connection with a bidirectional level translator to the microcontroller and a typical 11 kΩ pull-up to CVCC. |
| 5 | CCLK | output | Clock output to the card connector (C3), derived from CLKIN through the clock dividers and level shifter. |
| 6 | CRST | output | Reset output to the card (C2), level-shifted from RSTIN according to the programmed CVCC value. |
| 7 | CVCC | power_out | Card power supply output (C1) from the internal LDO programmable to 1.8 V, 3 V or 5 V, sourcing up to 70 mA and requiring 80 nF to 1.2 µF low-ESR (<100 mΩ) ceramic capacitance. |
| 8 | CMDVCC | input | Active-Low command VCC input; the activation sequence starts when CMDVCC toggles High to Low with a card present. |
| 9 | RSTIN | input | Reset input from the host referred to VDD, level-shifted to the card reset pin according to the programmed CVCC. |
| 10 | VDD | power_in | Controller-side supply, 2.7 V to 5.5 V, with a 0.1 µF decoupling capacitor; card pins are disabled when VDD falls below 2.30 V typical. |
| 11 | INT | output | Active-Low interrupt output that signals card presence and faults such as CVCC overload. |
| 12 | CLKIN | input | External clock input, up to 27 MHz. |
| 13 | I/Ouc | bidirectional | Microcontroller-side serial I/O with a bidirectional level translator to the card and a built-in constant 11 kΩ typical pull-up. |
| 14 | CLKDIV1 | input | Clock division ratio programming input, used together with CLKDIV2 (ratios 1, 1/2, 1/4, 1/8). |
| 15 | CLKDIV2 | input | Clock division ratio programming input, used together with CLKDIV1 (ratios 1, 1/2, 1/4, 1/8). |
| 16 | VSEL1 | input | Card VCC voltage select input: with VSEL0 Low, High gives 5 V and Low gives 3 V; with VSEL0 High, High gives 1.8 V and Low gives 3 V. |
| 17 | GND | power_in | Regulator power supply ground, connected to the exposed pad, which must be connected to the PCB. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | QFN-16-EP(3x3) |
| Category | Interface ICs |
| Pins | 17 |
## CAD (KiCad official)
- Symbol: `NCN8025MTTBG`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `ncn8025mttbg-etched.step` / `ncn8025mttbg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncn8025mttbg.step` / `ncn8025mttbg.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncn8025mttb-d.pdf) (15 pp, sha256 `c26d5c0564f47926`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ncn8025mttbg-datasheet.pdf)