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NCN26010XMNTXG

Public Made by Adom

by adom

onsemi Ethernet ICs, QFN-32(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ncn26010xmntxgfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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NCN26010XMNTXG

onsemi · Ethernet ICs · QFN-32(4x4)

NCN26010XMNTXG from onsemi, in a QFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XO output XTAL oscillator output: connects to one pin of a quartz crystal when a crystal is the clock source, and must be left floating (no connect) when an external clock is used.
2 XI input XTAL system clock input, optionally connected to an external crystal or a 3.3 V LVCMOS reference clock signal (25 MHz, ±100 ppm).
3 GND power_in Analog ground.
4 VDD power_in 3.3 V chip supply; recommended operating range 2.97 V to 3.63 V, absolute maximum −0.3 V to 3.63 V.
5 GND power_in Ground.
6 LINEP bidirectional Positive MDI data line of the 10BASE-T1S differential pair; absolute maximum line voltage −30 V to 30 V.
7 LINEN bidirectional Negative MDI data line of the 10BASE-T1S differential pair; absolute maximum line voltage −30 V to 30 V.
8 VDRVN bidirectional TX driver regulator output; connect to an off-chip 2.2 µF decoupling capacitor.
9 GND power_in Ground.
10 GND power_in Ground.
11 LED1/DIO1 output General-purpose I/O (8X LVCMOS) with programmable pull-up/pull-down that can drive an external LED through a bias resistor or other circuitry.
12 LED0/DIO0 output General-purpose I/O (8X LVCMOS) with programmable pull-up/pull-down that can drive an external LED through a bias resistor or other circuitry.
13 RSTn bidirectional Active-low asynchronous reset (8X open-drain, Schmitt-trigger) with internal pull-up of 54 kΩ typical; onsemi recommends an external 10 kΩ pull-up to VDDIO in noise-sensitive applications, and any driver must be open drain.
14 GND power_in Ground.
15 SCLK input SPI clock input with Schmitt-trigger input.
16 IRQn output Active-low interrupt request (4X open-drain), configurable to trigger on various events.
17 VDDIO power_in Digital I/O supply: 3.3 V (2.97 V to 3.63 V) or 2.5 V (2.25 V to 2.75 V) to support 2.5 V LVCMOS.
18 MOSI input SPI data input with Schmitt-trigger input.
19 CSn input Active-low SPI chip select input with Schmitt-trigger input; selects the device for SPI communication.
20 CLKO output 25 MHz clock output (4X LVCMOS) for other devices; designed to drive a maximum of four LVCMOS input loads, and an external clock buffer is recommended when driving 2.5 V I/O.
21 VDDIO power_in Digital I/O supply: 3.3 V (2.97 V to 3.63 V) or 2.5 V (2.25 V to 2.75 V) to support 2.5 V LVCMOS.
22 GND power_in Ground.
23 MISO output SPI data output (8X LVCMOS).
24 GND power_in Ground.
25 NC unconnected Do not connect.
26 NC unconnected Do not connect.
27 NC unconnected Do not connect.
28 DVDD bidirectional Output of the LDO supplying the digital core; connect to 2.2 µF decoupling capacitance.
29 DVDD bidirectional Always connect to pin 28 in the application.
30 GND power_in Ground.
31 GND power_in Ground.
32 NC unconnected Reserved; do not connect in the application.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer onsemi
Package QFN-32(4x4)
Category Communication Interface Chip/UART/485/232
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Chip Supply (absolute maximum) VDD -0.3 3.63 V 5
Ground (absolute maximum) GND -0.3 0 V 5
Storage Temperature Range TSTG -65 150 °C 5
Lead Temperature, Soldering TSLD 260 °C 10 Sec. 5
Line Voltage P LINEP -30 30 V 5
Line Voltage N LINEN -30 30 V 5
ESD Capability, Human Body Model ESDHBM 2 kV Human Body Model per JESD22-A114, TA = 25°C (Note 1) 5
ESD Capability for LINEP and LINEN Pins, Human Body Model ESDHBM_LINE 8 kV Human Body Model per JESD22-A114, TA = 25°C (Note 1) 5
ESD Capability, Charged Device Model ESDCDM 0.5 kV Charged Device Model per ESD STM5.3.1, TA = 25°C (Note 1) 5
Latch-up Current Immunity LU 100 mA Latch-up Current per JESD78, TA = 25°C (Note 1) 5
Chip Supply VDD 2.97 3.3 3.63 V 5
I/O Supply for 3.3 V Operation VDDIO 2.97 3.3 3.63 V 5
I/O Supply for 2.5 V Operation VDDIO 2.25 2.5 2.75 V 5
Ambient Operating Temperature TAMB -40 125 °C 5
Power Consumption (Transmitting and Receiving Ethernet Packets) PACTIVE 150 215 mW VDDIO = VDD = 3.3 V ±10% 6
XTAL Clock Frequency (tolerance around nominal 25 MHz) FXTAL -100 100 ppm VDD = VDDIO = 3.3 V ±10%; nominal 25 MHz 6
External Clock Frequency (tolerance around nominal 25 MHz) FEXT -100 100 ppm VDD = 3.3 V ±10%, VDDIO = 2.5 V ±10%; nominal 25 MHz 6
SPI Clock Frequency FSPI 25 MHz VDD = VDDIO = 3.3 V ±10% 6
SPI Clock Frequency FSPI 20 MHz VDD = 3.3 V ±10%, VDDIO = 2.5 V ±10% 6
Data Rate (10BASE-T1S) BITf 10 Mb/s 6
Peak Differential Output (Peak-to-peak) VOUTpp 800 1000 1200 mV VDD = 3.3 V ±10%, TX_GAIN = default (Note 2) 6
Cycle-to-Cycle Jitter JTX 0.2 1 ns 6
Output Impedance ROUT 40 50 60 VDD = 3.3 V ±10% 6
Threshold Accuracy Vacc -30 30 mV 6
Common Mode Voltage Range VCM -20 20 V 6
Differential Input Resistance RIN 25 40 60 k Driver is High-Z (Not Transmitting) 6
Differential Input Capacitance CIN 5.5 7.5 pF at 20 MHz 6
LVCMOS Input Level Low VIL -0.3 0.7 V VDDIO = 2.5 V ±10% 6
LVCMOS Input Level Low VIL -0.3 0.8 V VDDIO = 3.3 V ±10% 6
LVCMOS Input Level High VIH 1.7 V VDDIO = 2.5 V ±10% 6
LVCMOS Input Level High VIH 2 V VDDIO = 3.3 V ±10% 6
Schmitt Trigger Input Level Low Vt−(VIL) 0.7 1.5 V VDDIO = 2.5 V ±10% 6
Schmitt Trigger Input Level Low Vt−(VIL) 0.7 1.9 V VDDIO = 3.3 V ±10% 6
Schmitt Trigger Input Level High Vt+(VIH) 0.9 1.7 V VDDIO = 2.5 V ±10% 6
Schmitt Trigger Input Level High Vt+(VIH) 0.9 2.1 V VDDIO = 3.3 V ±10% 6
Schmitt Trigger Input Hysteresis Vhyst (/Vt+−Vt−/) 0.2 1 V VDDIO = 2.5 V ±10% 7
Schmitt Trigger Input Hysteresis Vhyst (/Vt+−Vt−/) 0.2 1.4 V VDDIO = 3.3 V ±10% 7
Output Level Low, 4X-Type VOL 0 0.45 V VDDIO = 2.5 V −10%, IOL = 2.48 mA (Note 3) 7
Output Level Low, 8X-Type VOL 0 0.45 V VDDIO = 2.5 V −10%, IOL = 4.83 mA 7
Output Level Low, 4X-Type VOL 0 0.4 V VDDIO = 3.3 V −10%, IOL = 2.93 mA 7
Output Level Low, 8X-Type VOL 0 0.4 V VDDIO = 3.3 V −10%, IOL = 5.65 mA 7
Input Current Low IIL -11 11 A 0.0 V ≤ Vin ≤ VDDIO, max supply = 3.63 V 7
Input Current High IIH -11 11 A 0.0 V ≤ Vin ≤ VDDIO, max supply = 3.63 V 7
Pull-Up Resistance RPU 33 54 103 k 7
Pull-Down Resistance RPD 30 44 73 k 7
SPI Clock Period tclkp 40 ns VDDIO = 2.25 V − 3.63 V 8
Data Input Setup Time tsu 8 ns VDDIO = 2.25 V − 3.63 V 8
Data Input Hold Time thd 5 ns VDDIO = 2.25 V − 3.63 V 8
Output Data Valid tdv 12 ns VDDIO = 3.3 V ±10% 8
Output Data Valid tdv 14.5 ns VDDIO = 2.5 V ±10% 8
CS Low to MISO Out Valid totv 12 ns VDDIO = 3.3 V ±10% 8
CS Low to MISO Out Valid totv 14.5 ns VDDIO = 2.5 V ±10% 8
CS Low to Rising Edge of SCLK tfc 20 ns VDDIO = 2.25 V − 3.63 V 8
SCLK Falling to CS De-assert tcsh 5 ns VDDIO = 2.25 V − 3.63 V 8
SCLK Falling to CS De-assert tcsh 5 14.5 ns VDDIO = 2.5 V ±10% 8
CS De-assert to MISO HIGH-Z tdz 12 ns VDDIO = 3.3 V ±10% 8
CS De-assert to MISO HIGH-Z tdz 14.5 ns VDDIO = 2.5 V ±10% 8
Junction-to-Ambient, Still Air (NCN26010XMNTXG) JA 56.5 K/W Still air; NCN26010XMNTXG 5

CAD (KiCad official)

  • Symbol: NCN26010XMNTXG
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: QFN-32(4x4) (KiCad packages3D, STEP)
  • 3D model files: ncn26010xmntxg-etched.step / ncn26010xmntxg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncn26010xmntxg.step / ncn26010xmntxg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (57 pp, sha256 b012d85d9428e0c5, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF