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NCL2801CFADR2G

Public Made by Adom

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onsemi Battery Management ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsncl2801cfadr2gfactory-2.0.0extractor-text
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3D Model

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Contents

README

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NCL2801CFADR2G

onsemi · Battery Management ICs · SOIC-8

NCL2801CFADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FB input Receives a portion of the PFC output voltage for regulation, DRE, soft/fast OVP and UVP (UVP threshold VUVPH 450 mV typ); a 250-nA sink current disables the part if the pin is left open.
2 VCTRL output Error amplifier output for the loop compensation network (bandwidth typically below 20 Hz); internally pulled down when off for soft-start and must not be controlled or pulled down externally.
3 MULT input Multiplier input receiving the scaled-down rectified mains voltage from a resistor divider between Vin and GND; the controller is not allowed to start if left open and is disabled above 3.2 V typ.
4 CS input Senses the MOSFET current to end the on-time at the control value or maximum current limit, and before startup senses the resistance to GND (RCS) to set the CrM-to-DCM VCTRL threshold.
5 ZCD input Uses the auxiliary winding voltage to determine the inductor current zero crossing (thresholds 750 mV rising and 250 mV falling typ).
6 GND power_in Connect this pin to the PFC stage ground.
7 DRV output Totem-pole gate drive with -0.5 A / +0.8 A capability to drive high gate charge power MOSFETs.
8 VCC power_in Positive supply of the IC; for the F option it starts at 10.5 V and turns off below 9.0 V typ, with operating range up to 27 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Input VCC -0.3 27 V 4
Feedback Pin FB -0.3 9 V 4
Multiplier Input pin MULT -0.3 9 V 4
CS Pin CS -0.3 9 V 4
Driver Current -500 800 mA 4
ZCD Pin ZCD -0.3 V max printed as VCC+0.3 4
Maximum Power Dissipation PD 300 mW TA=70°C 4
Thermal Resistance Junction to Air Rja 180 °C/W 4
Operating Junction Temperature Range TJ -40 125 °C 4
Maximum Junction Temperature TJ,max 150 °C 4
Storage Temperature Range TS,max -65 150 °C 4
Start-Up Threshold, VCC increasing VCC,on 9.75 10.5 11.25 V E & F Versions 5
Minimum Operating Voltage, VCC falling VCC,off 8.4 9 9.6 V A & B & E & F 5
Voltage at which IC completely restarts VCC,rst 6.5 7.2 7.8 V ICC drops to ~ ICC,start 5
Hysteresis (VCC,on - VCC,off) VCC,hyst 0.75 1.6 3 V E & F Versions 5
Start-Up Current ICC,start 0 10 60 µA VCC = 9.4 V, below startup voltage 5
Operating Consumption, no switching ICC,op1 0 0.4 1 mA 5
Operating Consumption, 50-kHz switching ICC,op2 1 2 3 mA no load on DRV pin 5
Output voltage rise-time tR 15 30 90 ns CL = 1 nF, 10-90% of output signal 5
Output voltage fall-time tF 10 20 50 ns CL = 1 nF, 10-90% of output signal 5
Source resistance ROH 4 10 20 Ω @ 200 mV under High VCC 5
Sink resistance ROL 2 7 15 Ω @ 200mV above Low VCC 5
DRV pin level, VCC = VCC,off + 200 mV VDRV,low 8.6 9.2 10 V 10-k resistor between DRV and GND; A & B & E & F 5
DRV pin level at VCC = 27 V VDRV,high 10 12 14 V RL = 33 k & CL = 1 nF 5
Maximum DRV voltage forcing zero at DRV VDRV,L 0 100 200 mV injecting 10 mA into DRV pin @ VCC = 12 V 5
Feedback Voltage Reference VREF 2.45 2.5 2.55 V 5
Error Amplifier Current Capability IEA 15 20 25 µA source and sink 5
Error Amplifier Gain GEA 110 200 290 µS 5
VCTRL pin Voltage high Vctrl,max 4.4 4.5 4.6 V @ VFB = 2 V (OTA is sourcing 20 µA) 5
VCTRL pin Voltage low Vctrl,min 0.4 0.5 0.6 V @ VFB = 3 V (OTA is sinking 20 µA) 5
Current Sense Voltage Reference when Low Line is detected VCS_OCP_LL(th) 0.97 1.07 1.19 V [**A]&[**C] Options; At tLEB,OCP 5
Current Sense Overstress Voltage Reference when Low Line is detected VCS_OVS_LL(th) 1.45 1.6 1.78 V [**A]&[**C] Options; At tLEB,OVS 5
Current Sense Voltage Reference when High Line is detected VCS_OCP_HL(th) 0.53 0.58 0.66 V [**A]&[**C] Options; At tLEB,OCP 6
Current Sense Overstress Voltage Reference when High Line is detected VCS_OVS_HL(th) 0.79 0.87 0.97 V [**A]&[**C] Options; At tLEB,OVS 6
Leading edge Blanking Time for current control tLEB,OCP 125 200 275 ns 6
Leading edge Blanking Time for Overstress tLEB,OVS 50 100 150 ns 6
Over-Current Protection Delay tOCP 10 40 200 ns from VCS>VCS(th) to DRV low; VCS > VCS + 100 mV 6
Watch Dog Timer in OverStress Situation tWDG(OS) 400 800 1200 µs 6
ZCD positive clamp VCL(pos) 12.6 12.9 13.2 V VCC = 12 V, IZCD = 5 mA 6
Zero Current Detection, VZCD rising VZCD(th)H 675 750 825 mV 6
Zero Current Detection, VZCD falling VZCD(th)L 200 250 300 mV 6
Hysteresis of the Zero Current Detection Comparator VZCD(hyst) 375 500 625 mV 6
ZCD pin input leakage current IZCD,bias 0 250 500 nA 6
ZCD to DRV high delay tZCD 20 80 200 ns (VZCD < VZCD(th)L) to (DRV high) 6
Watch Dog Timer tWDG 80 200 320 µs If no ZCD detected 6
Pull-up current source to detect ZCD open pin IZCD,pu 0.85 1 1.15 µA At startup only 6
Voltage reference to test ZCD pin short during startup VREF,ZCD,open 150 200 250 mV 6
Multiplier Gain when High Line is detected Kmult,HL 0.22 0.24 0.28 1/V [**A]&[**C] Options 6
Multiplier Gain when Low Line is detected Kmult,LL 0.72 0.8 0.88 1/V [**A]&[**C] Options 6
Ratio between Kmult,LL and Kmult,HL Kmult,Ratio 2.9 3.3 3.7 [**A]&[**C] Options 6
Koffset.Vton voltage added at multiplier output Koffset 0.1 0.14 0.2 [**A]&[**C] Options (w/ Line Detection) 6
Current pull-down on Mult pin Imult_pd 200 280 350 nA 6
Maximum MULT pin voltage Vmult_max 2.88 3.2 3.52 V Controller disabled if MULT pin voltage goes above this threshold 6
Maximum on-time tON,max,A,2 26 30 36 µs @ VCTRL = 4.50 V 6
Maximum on-time tON,max,A,1 3.6 5 6.9 µs @ VCTRL = 0.55 V 6
Soft OVP Threshold, VFB rising, over VREF RsoftOVP,C 103.5 105 106.5 % Options [C**] 8
Fast OVP Threshold, VFB rising, over VREF RfastOVP,C 103.2 107 110.8 % Option [C**] 8
DRE Threshold, VFB falling, over VREF RDRE 94 95.7 97.5 % 8
UVP Threshold, VFB increasing VUVPH 380 450 520 mV 8
Brown-In Threshold, Vmains increasing VBOH 725 787 860 mV 9
Brown-Out Threshold, Vmains decreasing VBOL 634 709 770 mV 9

CAD (KiCad official)

  • Symbol: NCL2801CFADR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncl2801cfadr2g-etched.step / ncl2801cfadr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncl2801cfadr2g.step / ncl2801cfadr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (28 pp, sha256 4746bd846f36d1af, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF