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NCEP40T13GU
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Wuxi NCE Power Semiconductor MOSFETs, DFN5X6-8L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCEP40T13GU
Wuxi NCE Power Semiconductor · MOSFETs · DFN5X6-8L
NCEP40T13GU from Wuxi NCE Power Semiconductor, in a DFN5X6-8L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins 2 and 3. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins 1 and 3. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins 1 and 2. |
| 4 | G | input | Gate terminal; VGS is rated ±20 V maximum, with threshold VGS(th) of 1.2 V min to 2.2 V max at ID=250μA. |
| 5 | D | passive | Drain terminal, tied to pins 6-8 and the exposed drain pad; VDS is rated 40 V maximum. |
| 6 | D | passive | Drain terminal, tied to pins 5, 7, 8 and the exposed drain pad; VDS is rated 40 V maximum. |
| 7 | D | passive | Drain terminal, tied to pins 5, 6, 8 and the exposed drain pad; VDS is rated 40 V maximum. |
| 8 | D | passive | Drain terminal, tied to pins 5-7 and the exposed drain pad; VDS is rated 40 V maximum. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi NCE Power Semiconductor |
| Package | DFN5X6-8L |
| Category | Transistors/Thyristors |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | 40 | V | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Drain Current-Continuous (Silicon Limited) | ID | 130 | A | Silicon limited | 1 | ||
| Drain Current-Continuous (TC=100℃) | ID(100℃) | 100 | A | TC=100℃ | 1 | ||
| Pulsed Drain Current (Package Limited) | IDM | 400 | A | Package limited | 1 | ||
| Maximum Power Dissipation | PD | 80 | W | TC=25℃ | 1 | ||
| Single pulse avalanche energy (Note 5) | EAS | 600 | mJ | Note 5: Tj=25℃, VDD=20V, VG=10V, L=0.5mH, Rg=25Ω | 1 | ||
| Operating Junction and Storage Temperature Range | TJ,TSTG | -55 | 150 | ℃ | 1 | ||
| Drain-Source Breakdown Voltage | BVDSS | 40 | V | VGS=0V ID=250μA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | μA | VDS=40V,VGS=0V | 2 | ||
| Gate-Body Leakage Current | IGSS | -100 | 100 | nA | VGS=±20V,VDS=0V | 2 | |
| Gate Threshold Voltage | VGS(th) | 1.2 | 1.7 | 2.2 | V | VDS=VGS,ID=250μA | 2 |
| Drain-Source On-State Resistance (VGS=10V) | RDS(ON) | 1.8 | 2.3 | mΩ | VGS=10V, ID=65A | 2 | |
| Drain-Source On-State Resistance (VGS=4.5V) | RDS(ON) | 2.8 | 3.6 | mΩ | VGS=4.5V, ID=65A | 2 | |
| Input Capacitance | Clss | 3334 | 3990 | PF | 2 | ||
| Output Capacitance | Coss | 650 | 750 | PF | 2 | ||
| Reverse Transfer Capacitance | Crss | 57 | 68 | PF | VDS=20V,VGS=0V, F=1.0MHz | 2 | |
| Total Gate Charge | Qg | 49 | 70 | nC | 2 | ||
| Diode Forward Current (Note 2) | IS | 130 | A | 2 | |||
| Thermal Resistance, Junction-to-Case (Note 2) | RθJC | 1.56 | ℃/W | Note 2: surface mounted on FR4 board, t ≤ 10 sec | 2 |
CAD (KiCad official)
- Symbol:
NCEP40T13GU - Footprint:
Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm - 3D model: DFN5X6-8L (KiCad packages3D, STEP)
- 3D model files:
ncep40t13gu-etched.step/ncep40t13gu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncep40t13gu.step/ncep40t13gu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi NCE Power Semiconductor datasheet (6 pp, sha256
b811db327d6a016b, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).