main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3h ago
viewers nce55p05s: viewers · Ray 3h ago
nce55p05s-etched.glb nce55p05s: factory component page (tier=lcsc) · Ray 3h ago
nce55p05s-etched.step nce55p05s: factory component page (tier=lcsc) · Ray 3h ago
nce55p05s-hero.glb nce55p05s: hero GLB from the etched model (keeps the MPN mark) · Ray 3h ago
nce55p05s-hero.overlay.json Publish 0.1.0 · Ray 3h ago
nce55p05s.glb Publish 0.1.0 · Ray 3h ago
nce55p05s.kicad_mod Publish 0.1.0 · Ray 3h ago
nce55p05s.kicad_sym Publish 0.1.0 · Ray 3h ago
nce55p05s.lbr Publish 0.1.0 · Ray 3h ago
nce55p05s.step Publish 0.1.0 · Ray 3h ago
package.json Publish 0.1.0 · Ray 3h ago
page.json Set visibility: public · Ray 3h ago
README.md Publish 0.1.0 · Ray 3h ago

NCE55P05S

Wuxi NCE Power Semiconductor · MOSFETs · SOP-8

NCE55P05S from Wuxi NCE Power Semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the P-channel MOSFET, tied to pins 2 and 3; drain-source voltage rated -55V.
2 S passive Source of the P-channel MOSFET, tied to pins 1 and 3; continuous drain current rated -5A.
3 S passive Source of the P-channel MOSFET, tied to pins 1 and 2; pulsed drain current up to -25A.
4 G input Gate of the P-channel MOSFET with gate-source voltage limit of ±20V and threshold of -1.5V to -3.5V.
5 D passive Drain of the P-channel MOSFET, tied to pins 6, 7 and 8; RDS(ON) below 80mΩ at VGS=-10V.
6 D passive Drain of the P-channel MOSFET, tied to pins 5, 7 and 8; drain-source voltage rated -55V.
7 D passive Drain of the P-channel MOSFET, tied to pins 5, 6 and 8; continuous drain current rated -5A.
8 D passive Drain of the P-channel MOSFET, tied to pins 5, 6 and 7; pulsed drain current up to -25A.

Key specifications

Parameter Value
Manufacturer Wuxi NCE Power Semiconductor
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: NCE55P05S
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: nce55p05s-etched.step / nce55p05s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nce55p05s.step / nce55p05s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi NCE Power Semiconductor datasheet (7 pp, sha256 76d0f0544a7fc57f, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF