component

NCD57200DR2G

Public Made by Adom

by adom

onsemi Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsncd57200dr2gfactory-2.0.0extractor-text

Verified NCD57200DR2G

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: NCD57200DR2G · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 18-page datasheet
  • ✓distributor: lcsc C904341, digikey 488-NCD57200DR2GTR-ND, mouser 863-NCD57200DR2G
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-8al6ryw4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.16)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ncd57200dr2g.kicad_sym✓ ncd57200dr2g.kicad_mod✓ ncd57200dr2g.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers ncd57200dr2g: viewers · Ray 8d ago
ncd57200dr2g-etched.glb Publish 0.1.0 · Ray 8d ago
ncd57200dr2g-etched.step ncd57200dr2g: factory component page (tier=mfr) · Ray 8d ago
ncd57200dr2g-hero.glb ncd57200dr2g: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
ncd57200dr2g-hero.overlay.json Publish 0.1.0 · Ray 8d ago
ncd57200dr2g.glb Publish 0.1.0 · Ray 8d ago
ncd57200dr2g.kicad_mod Publish 0.1.0 · Ray 8d ago
ncd57200dr2g.kicad_sym Publish 0.1.0 · Ray 8d ago
ncd57200dr2g.lbr Publish 0.1.0 · Ray 8d ago
ncd57200dr2g.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 8d ago

NCD57200DR2G

onsemi · Gate Drive ICs · SOIC-8

NCD57200DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Low side and main power supply that must be bypassed close to the pins to GND, with UVLO enabling operation once VDD rises above VUVLO1-OUT-ON and the recommended VDD range extending up to 20 V.
2 HIN input High side non-inverting gate driver input with an equivalent pull-down resistor of 125 k to keep HO low without input, 3.3 V logic thresholds for inputs up to VDD, and a minimum pulse width required before HO reacts.
3 LIN input Low side non-inverting gate driver input with an equivalent pull-down resistor of 125 k to keep LO low without input, 3.3 V logic thresholds for inputs up to VDD, and a minimum pulse width required before LO reacts.
4 GND power_in Logic ground and low side driver return.
5 LO output Low side driver output that provides gate drive and source/sink current to the IGBT, is actively pulled low during startup and under UVLO1, and has deadtime and interlock logic to prevent cross conduction with HO.
6 VS power_in Bootstrap return or high side floating supply offset, with recommended operating range of -800 V to 800 V and absolute maximum of -900 V to 900 V.
7 HO output Galvanically isolated high side driver output that provides gate drive and source/sink current to the IGBT, is actively pulled low during startup and under UVLOx, and has deadtime and interlock logic to prevent cross conduction with LO.
8 VB power_in Bootstrap or high side floating power supply that requires a bypass capacitor to VS placed close to the pins, with UVLO enabling operation once VBS rises above VUVLO2-OUT-ON and recommended VBS up to VS+20 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-Side Offset Voltage (see Figure 2) VS -900 900 V 4
High-Side Supply Voltage (see Figure 2) VB -900 900 V 4
Low-Side Supply Voltage VDD -0.3 25 V 4
High-Side Floating Supply Voltage VBS -0.3 25 V 4
Allowable Offset Voltage Slew Rate dVS/dt -100 100 V/ns 4
Maximum Junction Temperature TJ(max) -40 150 °C 4
Storage Temperature Range TSTG -65 150 °C 4
ESD Capability, Human Body Model ESDHBM -4 4 kV Human Body Model (Note 2) 4
ESD Capability, Charged Device Model ESDCDM -2 2 kV Charged Device Model (Note 2) 4
Lead Temperature Soldering Reflow (SMD Styles Only), Pb-Free Versions TSLD 260 °C Note 3 4
High-Side Offset Voltage (see Figure 2) VS -800 800 V 4
Low-Side Supply Voltage VDD 20 V 4
Ambient Temperature TA -40 125 °C 4
VBS Supply Under Voltage Output Enabled VUVLO2−OUT−ON 11 11.5 12 V 5
VBS Supply Under Voltage Output Disabled VUVLO2−OUT−OFF 10 10.5 11 V 5
VBS Supply Voltage Output Enabled/Disabled Hysteresis VUVLO2−HYST 0.5 1 1.2 V 5
VDD Supply Under Voltage Output Enabled VUVLO1−OUT−ON 12 12.5 13 V 5
VDD Supply Under Voltage Output Disabled VUVLO1−OUT−OFF 11 11.5 12 V 5
VDD Supply Voltage Output Enabled/Disabled Hysteresis VUVLO1−HYST 0.5 1 1.2 V 5
Leakage Current Between VS and GND IHV_LEAK1 20 200 nA VS = ±800 V, TA = 25°C 5
Leakage Current Between VS and GND IHV_LEAK2 600 nA VS = ±800 V, TA = −40°C to 125°C 5
Quiescent Current VBS Supply (VB Only) IQBS1 260 325 µA HO = Low 5
Quiescent Current VBS Supply (VB Only) IQBS2 330 440 µA HO = High 5
Quiescent Current VDD Supply (VDD Only) IQDD1 380 440 µA VLIN = Float, VHIN = 0 V 5
Quiescent Current VDD Supply (VDD Only) IQDD2 440 500 µA VLIN = 3.3 V, VHIN = 0 V 5
Quiescent Current VDD Supply (VDD Only) IQDD3 2.4 3 mA VLIN = 0 V, VHIN = 3.3 V 5
Low Level Input Voltage VIL 0.9 V 5
High Level Input Voltage VIH 2.4 V 5
Logic “1” Input Bias Current ILIN1+, IHIN1+ 25 50 µA VLIN = 3.3 V, VHIN = 3.3 V 5
Logic “1” Input Bias Current ILIN2+, IHIN2+ 100 150 µA VLIN = 20 V, VHIN = 20 V, VDD = VBS = 20 V 5
Logic “0” Input Bias Current ILIN−, IHIN− 40 100 nA VLIN = 0 V, VHIN = 0 V 5
Output Low State VOL1 0.2 0.3 V ISINK = 200 mA, TA = 25°C 5
Output Low State VOL2 0.5 V ISINK = 200 mA, TA = −40°C to 125°C 5
Output High State VOH1 14.4 14.5 V ISOURCE = 200 mA, TA = 25°C 5
Output High State VOH2 14 V ISOURCE = 200 mA, TA = −40°C to 125°C 5
Peak Driver Current, Sink (Note 7) IPK−SNK1 2.3 A VHO = VLO = 15 V 5
Peak Driver Current, Sink (Note 7) IPK−SNK2 2.1 A VHO = VLO = 9 V (near Miller Plateau) 5
Peak Driver Current, Source (Note 7) IPK−SRC1 1.9 A VHO = VLO = 0 V 5
Peak Driver Current, Source (Note 7) IPK−SRC2 1.5 A VHO = VLO = 9 V (near Miller Plateau) 5
Clamping Voltage (VHO, VB) / (VLO, VDD) VCLAMP−OUT 0.8 1.3 V IHO = 100 mA, ILO = 100 mA (pulse test, tCLPmax = 10 s) 6
HO High Propagation Delay tPD−ON−H 50 90 110 ns CLOAD = 1 nF, VIH to 10% of Output Change for PW > 150 ns 6
HO Low Propagation Delay tPD−OFF−H 50 90 110 ns CLOAD = 1 nF, VIL to 90% of Output Change for PW > 150 ns 6
Propagation Delay Distortion(HS) (= tPD−ON−H − tPD−OFF−H) tDISTORT−H -25 0 25 ns PW > 150 ns 6
LO High Propagation Delay tPD−ON−L 50 90 110 ns CLOAD = 1 nF, VIH to 10% of Output Change for PW > 150 ns 6
LO Low Propagation Delay tPD−OFF−L 50 90 110 ns CLOAD = 1 nF, VIL to 90% of Output Change for PW > 150 ns 6
Propagation Delay Distortion(LS) (= tPD−ON−L − tPD−OFF−L) tDISTORT−L -25 0 25 ns PW > 150 ns 6
High Propagation Delay Distortion between High and Low Sides tDISTORT−HL−H -25 0 25 ns PW > 150 ns 6
Low Propagation Delay Distortion between High and Low Sides tDISTORT−HL−L -25 0 25 ns PW > 150 ns 6
Rise Time (HO) (see Figure 3) tRISE−H 13 ns CLOAD = 1 nF, 10% to 90% of Output Change 6
Fall Time (HO) (see Figure 3) tFALL−H 8 ns CLOAD = 1 nF, 90% to 10% of Output Change 6
Rise Time (LO) (see Figure 3) tRISE−L 13 ns CLOAD = 1 nF, 10% to 90% of Output Change 6
Fall Time (LO) (see Figure 3) tFALL−L 8 ns CLOAD = 1 nF, 90% to 10% of Output Change 6
Deadtime Matching tMDT 10 ns 6
Minimum Pulse Width Filtering Time (see Figure 3) tMIN1, tMIN2 10 40 ns TA = 25°C 6
Deadtime, HO Delays (see Figure 6) tDT1 340 ns VLIN/HIN = 0 V and 3.3 V 6
Deadtime, LO Delays (see Figure 6) tDT2 350 ns VLIN/HIN = 0 V and 3.3 V 6
UVLO Fall Delay (HO and LO) tUVF1, tUVF2 1300 ns 6
UVLO Rise Delay (HO and LO) tUVR1, tUVR2 1100 ns 6
Thermal Resistance, Junction-to-Air (Note 5) RJA 167 °C/W Copper area 100 mm2 (0.16 in2), 1 oz copper, FR4 PCB 4

CAD (KiCad official)

  • Symbol: NCD57200DR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncd57200dr2g-etched.step / ncd57200dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncd57200dr2g.step / ncd57200dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (18 pp, sha256 51ed35afca0d8e18, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF