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NCD57085DR2G

Public Made by Adom

by adom

onsemi Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsncd57085dr2gfactory-2.0.0extractor-text
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Contents

README

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NCD57085DR2G

onsemi · Gate Drive ICs · SOIC-8

NCD57085DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Input side power supply (operating range UVLO1 to 20 V) that needs a good quality bypass capacitor to GND placed close to the pin.
2 IN input Non-inverted gate driver input with about 100 kΩ equivalent pull-down below 5.5 V, requiring a minimum pulse width before HO responds.
3 FLT output Active-low fault output with internal 50 kΩ pull-up that reports over current, UVLO1 or UVLO2 conditions and can be OR'ed with other drivers.
4 GND power_in Input side ground reference.
5 VS power_in Output side ground reference.
6 CS bidirectional Over current detection input for the IGBT with 0.25 V typical threshold that must be met for tFILTER before HO and FLT go low, with negative voltage capability down to -9 V.
7 HO output Driver output providing drive voltage and source/sink current (+7 A/-7 A peak) to the IGBT/FET gate, actively pulled low during start-up.
8 VB power_in Output side positive power supply (operating range UVLO2 to 30 V) that needs a good quality bypass capacitor to VS placed close to the pins.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
UVLO1 Output Enabled VUVLO1-OUT-ON 3.1 V VDD = 5 V, VBS = 15 V 8
UVLO1 Output Disabled VUVLO1-OUT-OFF 2.4 V VDD = 5 V, VBS = 15 V 8
UVLO1 Hysteresis VUVLO1-HYST 0.1 V 8
UVLO2 Output Enabled VUVLO2-OUT-ON 12.4 12.9 13.4 V 8
UVLO2 Output Disabled VUVLO2-OUT-OFF 11.5 12 12.5 V 8
UVLO2 Hysteresis VUVLO2-HYST 0.7 1 V 8
Input Supply Quiescent Current IDD-0-3.3 2 mA IN = Low, VDD = 3.3 V, FLT = High 8
Input Supply Current, IN high IDD-100-5 6 mA IN = High, VDD = 5 V, FLT = High 8
Output Supply Quiescent Current IBS-0 4 mA IN = Low, no load 8
Output Supply Current, IN high IBS-100 6 mA IN = High, no load 8
FLT Low Level Output Voltage VFLT-L 0.3 V IFLT = 5 mA 8
Input Pulse Width of IN for No Response tMIN1 10 ns 8
Input Pulse Width of IN for Guaranteed Response tMIN2 40 ns 8
Output Low State (VHO - VS) VHOL1 0.1 0.22 V ISNK = 200 mA 8
Output Low State (VHO - VS) VHOL2 0.4 1 V ISNK = 1.0 A, TA = 25°C 8
Output High State (VB - VHO) VHOH1 0.2 0.35 V ISRC = 200 mA 8
Output High State (VB - VHO) VHOH2 0.6 1.7 V ISRC = 1.0 A, TA = 25°C 8
CS Threshold Voltage VCS-THR 0.2 0.25 0.3 V 8
IGBT Short Circuit Clamping (VHO - VB) VCLP-HO 0.7 1.5 V IN = High, IHO = 500 mA, tCLP = 10 µs 9
IN to HO High Propagation Delay tPD-ON 40 60 90 ns CLOAD = 10 nF, VIH to 10% of HO Change for PW > 150 ns 9
IN to HO Low Propagation Delay tPD-OFF 40 60 90 ns CLOAD = 10 nF, VIL to 90% of HO Change for PW > 150 ns 9
Propagation Delay Distortion tDISTORT -25 25 ns TA = -40°C to 125°C, PW > 150 ns 9
Propagation Delay Distortion between Parts tDISTORT_TOT -30 0 30 ns PW > 150 ns 9
CS Leading Edge Blanking Time tLEB 200 450 700 ns 9
CS Threshold Filtering Time tFILTER 600 700 ns 9
Soft Turn Off Time tSTO 1.2 1.8 3 µs CLOAD = 10 nF, RG = 10 Ω 9
Delay after tFILTER to FLT Low tFLT 100 450 700 ns 9
IN Mute Time after tFILTER, or UVLO1, UVLO2 Triggered tMUTE 20 µs 9
Supply Voltage, Input Side (abs max) VDD-GND -0.3 22 V 7
Supply Voltage, Output Side (abs max) VB-VS -0.3 32 V 7
Gate-driver Output Voltage VHO-VS -0.3 V max VBS + 0.3 V 7
Gate-driver Output Sourcing Current IPK-SRC 7 A max pulse width = 10 µs, max duty cycle = 0.2%, VD - VS = 15 V 7
Gate-driver Output Sinking Current IPK-SNK 7.5 A max pulse width = 10 µs, max duty cycle = 0.2%, VD - VS = 15 V 7
Voltage at IN, FLT VIN-GND -0.3 V max VDD + 0.3 V 7
Output current of FLT IFLT 10 mA 7
Voltage at CS VCS-VS -9 V max VBS + 0.3 V 7
Power Dissipation PD 1123 mW TA 25°C, TJ 150°C, 650 mm2, 1 oz copper, 2 surface layers and 2 internal power plane layers 7
ESD Human Body Model ESDHBM -2 2 kV 7
ESD Charged Device Model ESDCDM -2 2 kV 7
Maximum Junction Temperature TJ(max) -40 150 °C 7
Storage Temperature Range TSTG -65 150 °C 7
Lead Temperature Soldering Reflow, Pb-Free TSLD 260 °C 7
Supply Voltage, Input Side (operating) VDD-GND 20 V min is UVLO1 7
Supply Voltage, Output Side (operating) VB-VS 30 V min is UVLO2 7
Logic Input Voltage at IN VIN 0 V GND to VDD 7
Common Mode Transient Immunity /dVISO/dt/ 100 kV/µs 7
Ambient Temperature TA -40 125 °C 7
Thermal Resistance, Junction-to-Air RθJA 179 °C/W 100 mm2, 1 oz Copper, 1 Surface Layer 7
Thermal Resistance, Junction-to-Air RθJA 110 °C/W 100 mm2, 1 oz Copper, 2 Surface Layers and 2 Internal Power Plane Layers 7
Peak Driver Current, Sink IPK-SNK1 7.5 A 8
Peak Driver Current, Source IPK-SRC1 7 A 8
Rise Time tRISE 10 ns CLOAD = 1 nF, 10% to 90% of HO Change 9
Fall Time tFALL 15 ns CLOAD = 1 nF, 90% to 10% of HO Change 9
CS Negative Voltage VCS-NEG -8 V ICS = 1.5 mA 8
Input-Output Isolation Voltage VISO,INPUT-OUTPUT 2500 VRMS TA = 25°C, RH < 50%, t = 1.0 minute, II-O < 30 µA, 50 Hz 6

CAD (KiCad official)

  • Symbol: NCD57085DR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncd57085dr2g-etched.step / ncd57085dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncd57085dr2g.step / ncd57085dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (23 pp, sha256 93bf8773284ece5c, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF