component

NCD5701BDR2G

Public Made by Adom

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onsemi Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsncd5701bdr2gfactory-2.0.0extractor-text

Verified NCD5701BDR2G

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: NCD5701BDR2G · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C603416, digikey NCD5701BDR2GOSTR-ND, mouser 863-NCD5701BDR2G
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-lnll02n2/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ncd5701bdr2g.kicad_sym✓ ncd5701bdr2g.kicad_mod✓ ncd5701bdr2g.step
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Ray Publish 0.1.0 93f5b8e 8d ago

NCD5701BDR2G

onsemi · Gate Drive ICs · SOIC-8

NCD5701BDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input signal controlling the output, internally clamped to 5.5 V with a 1 MΩ pull-up to VREF so the output is low without input, and requires a minimum pulse width before VO is activated.
2 VREF power_in Internally generated 5 V reference (4.85 V to 5.15 V at IREF = 10 mA) brought out for bypassing and for powering low-bias circuits, with at least 100 nF recommended and up to 20 mA output current.
3 FLT output Active-low fault output that signals the controller when the driver has detected a fault and deactivated the output, capable of driving optos or digital isolators.
4 DESAT input Desaturation detection input where a capacitor sets a programmable blanking delay each ON cycle before a DESAT fault is processed; DESAT threshold is 6.0 V to 7.0 V.
5 VCC power_in Positive bias supply for the driver, operating from the UVLO threshold up to the maximum rating of 22 V (VCC-GND), and requires a bypass capacitor to GND placed close to the pin.
6 VO output Driver output that provides gate drive voltage with source and sink current to the IGBT gate and is actively pulled low during start-up and fault conditions.
7 GND power_in Reference ground that must connect to the IGBT emitter with a short trace, with all power pin bypass capacitors referenced to this pin.
8 VEE power_in Optional negative supply for the NCD5701B that allows VO to swing negative during OFF state (VEE-GND from -18 V to 0.3 V absolute maximum); if no negative voltage is used this pin must be connected to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential Power Supply VCC−VEE (Vmax) 0 36 V 7
Positive Power Supply VCC−GND -0.3 22 V 7
Negative Power Supply VEE−GND -18 0.3 V 7
Input Voltage VIN−GND -0.3 5.5 V 7
FLT current Sink IFLT−SINK 20 mA 7
FLT current Source IFLT−SRC 25 mA 7
Power Dissipation SO-8 package PD 700 mW 7
Maximum Junction Temperature TJ(max) 150 °C 7
Storage Temperature Range TSTG -65 150 °C 7
ESD Capability, Human Body Model ESDHBM 4 kV 7
ESD Capability, Machine Model ESDMM 200 V 7
Lead Temperature Soldering Reflow (Pb-Free) TSLD 260 °C 7
Thermal Resistance, Junction-to-Air SOIC-8 RJA 176 °C/W Copper area 100 mm2 of 1 oz copper, FR4 PCB 7
Differential Power Supply VCC−VEE (Vmax) 30 V 7
Negative Power Supply VEE -15 0 V 7
Input Voltage VIN 0 5 V 7
Input pulse width ton 40 ns 7
Ambient Temperature TA -40 125 °C 7
Input Pulse-Width No Response at the Output ton−min1 30 ns Voltage thresholds consistent with input specs 8
Input Pulse-Width Guaranteed Response at the Output ton−min2 10 ns Voltage thresholds consistent with input specs 8
FLT Threshold Voltage Low State VFLT−L 0.5 1 V IFLT−SINK = 15 mA 8
FLT Threshold Voltage High State VFLT−H 12 13.9 V IFLT−SRC = 20 mA 8
Output Low State VOL1 0.1 0.2 V Isink = 200 mA, TA = 25°C 8
Output Low State VOL2 0.2 0.5 V Isink = 200 mA, TA = −40°C to 125°C 8
Output Low State VOL3 0.8 1.2 V Isink = 1.0 A, TA = 25°C 8
Output High State VOH1 14.5 14.8 V Isrc = 200 mA, TA = 25°C 8
Output High State VOH2 14.2 14.7 V Isrc = 200 mA, TA = −40°C to 125°C 8
Output High State VOH3 13.8 14.1 V Isrc = 1.0 A, TA = 25°C 8
Peak Driver Current, Sink IPK−snk1 6.8 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = 13 V 8
Peak Driver Current, Sink IPK−snk2 6.1 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = 9 V (near Miller Plateau) 8
Peak Driver Current, Source IPK−src1 7.8 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = −5 V 8
Peak Driver Current, Source IPK−src2 4 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = 9 V (near Miller Plateau) 8
Turn-on Delay tpd−on 45 56 75 ns Negative input pulse width = 10 s 8
Turn-off Delay tpd−off 45 63 75 ns Positive input pulse width = 10 s 8
Propagation Delay Distortion tdistort2 -25 25 ns For input or output pulse width > 150 ns, TA = −40°C to 125°C 8
Prop Delay Distortion between Parts tdistort−tot -30 0 30 ns 8
DESAT Threshold Voltage VDESAT−THR 6 6.35 7 V 8
Blanking Charge Current IDESAT−CHG 0.2 0.24 0.28 mA 8
UVLO Startup Voltage VUVLO−OUT−ON 13.2 13.5 13.8 V 8
UVLO Disable Voltage VUVLO−OUT−OFF 12.2 12.5 12.8 V 8
Voltage Reference VREF 4.85 5 5.15 V IREF = 10 mA 8
Current Drawn from VCC Standby ICC−SB 0.9 1.5 mA VCC = 15 V; standby (no load on output, FLT, VREF) 9
Current Drawn from VEE (NCD5701B only) Standby IEE−SB -0.2 -0.14 mA VEE = −10 V; standby (no load on output, FLT, VREF) 9
Delay from FLT under UVLO/TSD to VO/VOL td1−OUT 10 12 15 µs 8

CAD (KiCad official)

  • Symbol: NCD5701BDR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncd5701bdr2g-etched.step / ncd5701bdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncd5701bdr2g.step / ncd5701bdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (20 pp, sha256 ea9003fdf65bc54d, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF