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NCD5701ADR2G

Public Made by Adom

by adom

onsemi Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsncd5701adr2gfactory-2.0.0extractor-text
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Contents

README

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NCD5701ADR2G

onsemi · Gate Drive ICs · SOIC-8

NCD5701ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input signal that controls the output with signal inversion from VIN to VO, internally clamped to 5.5 V with a 1 MΩ pull-up to VREF so the output stays low when no input is applied, and a minimum pulse width is required before VO activates.
2 VREF power_in Internally generated 5 V reference brought out for external bypassing and low-bias circuits, rated 4.85 V to 5.15 V at IREF = 10 mA and to be bypassed with at least 100 nF.
3 FLT output Active-low fault output that tells the controller the driver has encountered a fault and deactivated the output, with absolute limits of 20 mA sink and 25 mA source.
4 DESAT input Input for detecting IGBT desaturation, where a capacitor on this pin sets a programmable blanking delay each ON cycle and the DESAT threshold is 6.0 V to 7.0 V (6.35 V typical).
5 VCC power_in Positive bias supply for the driver, whose operating range runs from the UVLO level up to the maximum, with an absolute limit of −0.3 V to 22 V versus GND and a bypass capacitor required close to the pin.
6 VO output Gate driver output that sources and sinks current to the IGBT gate and is actively pulled low during start-up and fault conditions, with VO limited to VEE − 0.3 V minimum and VCC + 0.3 V maximum.
7 GND power_in Reference ground that must connect to the IGBT emitter with a short trace, with all power-pin bypass capacitors referenced to and kept close to this pin.
8 CLAMP bidirectional Active Miller clamp that holds the IGBT gate low during the off period to prevent parasitic turn-on and must be tied directly to the IGBT gate with minimum trace length, clamping at 1.4 V typical at 500 mA and activating at VMC-THR of 1.8 V to 2.2 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential Power Supply VCC-VEE (Vmax) 0 36 V 7
Positive Power Supply VCC-GND -0.3 22 V 7
Negative Power Supply VEE-GND -18 0.3 V 7
Input Voltage VIN-GND -0.3 5.5 V 7
DESAT Voltage VDESAT-GND -0.3 V Maximum printed as VCC + 0.3 V (not numeric) 7
FLT current Sink IFLT-SINK 20 mA 7
FLT current Source IFLT-SRC 25 mA 7
Power Dissipation SO-8 package PD 700 mW 7
Maximum Junction Temperature TJ(max) 150 °C 7
Storage Temperature Range TSTG -65 150 °C 7
ESD Capability, Human Body Model ESDHBM 4 kV Per AEC-Q100-002 (EIA/JESD22-A114) 7
Positive Power Supply VCC UVLO (operating range lower limit) VCC UVLO 20 V 7
Negative Power Supply VEE -15 0 V 7
Input Voltage VIN 0 5 V 7
Input pulse width ton 40 ns 7
Ambient Temperature TA -40 125 °C 7
Input Threshold Voltage High-state (Logic 1) Required VIN-H1 4.3 V Pulse-Width = 150 ns, VEN = 5 V 8
Input Threshold Voltage Low-state (Logic 0) Required VIN-L1 1.2 V Pulse-Width = 150 ns, VEN = 5 V 8
Input Voltage No state change VIN-NC 0.75 3.7 V Pulse-Width = 150 ns, VEN = 5 V 8
Input Current High-state IIN-H 1 A VIN-H = 4.5 V (unit printed as 'A', micro prefix lost in text) 8
Input Current Low-state IIN-L 10 A VIN-L = 0.5 V (unit printed as 'A', micro prefix lost in text) 8
Input Pulse-Width No Response at the Output ton-min1 30 ns No Response at the Output 8
Input Pulse-Width Guaranteed Response at the Output ton-min2 10 ns Guaranteed Response at the Output 8
FLT Threshold Voltage Low State VFLT-L 0.5 1 V IFLT-SINK = 15 mA 8
FLT Threshold Voltage High State VFLT-H 12 13.9 V IFLT-SRC = 20 mA 8
Output Low State VOL1 0.1 0.2 V Isink = 200 mA, TA = 25°C 8
Output Low State VOL2 0.2 0.5 V Isink = 200 mA, TA = −40°C to 125°C 8
Output Low State VOL3 0.8 1.2 V Isink = 1.0 A, TA = 25°C 8
Output High State VOH1 14.5 14.8 V Isrc = 200 mA, TA = 25°C 8
Output High State VOH2 14.2 14.7 V Isrc = 200 mA, TA = −40°C to 125°C 8
Output High State VOH3 13.8 14.1 V Isrc = 1.0 A, TA = 25°C 8
Turn-on Delay tpd-on 45 56 75 ns Negative input pulse width = 10 s 8
Turn-off Delay tpd-off 45 63 75 ns Positive input pulse width = 10 s 8
Propagation Delay Distortion tdistort1 -15 5 ns Input or output pulse width > 150 ns, TA = 25°C 8
Propagation Delay Distortion tdistort2 -25 25 ns Input or output pulse width > 150 ns, TA = −40°C to 125°C 8
Prop Delay Distortion between Parts tdistort-tot -30 0 30 ns 8
Delay from FLT under UVLO/TSD to VO/VOL td1-OUT 10 12 15 s 8
Clamp Voltage Vclamp 1.2 1.4 V Isink = 500 mA, TA = 25°C 9
Clamp Voltage Vclamp 2.2 V Isink = 500 mA, TA = −40°C to 125°C 9
Clamp Activation Threshold VMC-THR 1.8 2 2.2 V 9
DESAT Threshold Voltage VDESAT-THR 6 6.35 7 V 9
Blanking Charge Current IDESAT-CHG 0.2 0.24 0.28 mA 9
UVLO Startup Voltage VUVLO-OUT-ON 13.2 13.5 13.8 V 9
UVLO Disable Voltage VUVLO-OUT-OFF 12.2 12.5 12.8 V 9
Voltage Reference VREF 4.85 5 5.15 V IREF = 10 mA 9
Current Drawn from VCC Standby (No load on output, FLT, VREF) ICC-SB 0.9 1.5 mA VCC = 15 V 9
Input Internal Pull-Up Resistance to VREF RIN-H 1 M 8
Peak Driver Current, Sink IPK-snk1 6.8 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = 13 V 8
Peak Driver Current, Sink IPK-snk2 6.1 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = 9 V (near Miller Plateau) 8
Peak Driver Current, Source IPK-src1 7.8 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = −5 V 8
Peak Driver Current, Source IPK-src2 4 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = 9 V (near Miller Plateau) 8
Rise Time trise 9.2 ns Cload = 1.0 nF 8
Fall Time tfall 7.9 ns Cload = 1.0 nF 8
Delay from DESAT to VO/VOL td2-OUT 220 ns 9
Delay from UVLO/TSD to FLT td3-FLT 7.3 s 9
Blanking Discharge Current IDESAT-DIS 30 mA 9
UVLO Hysteresis VUVLO-HYST 1 V 9
Thermal Shutdown Temperature TSD 188 °C 9
Thermal Shutdown Hysteresis TSH 33 °C 9
Thermal Resistance, Junction-to-Air, SOIC-8 RJA 176 °C/W Copper area 100 mm2 (0.16 in2), 1 oz copper, FR4 PCB 7

CAD (KiCad official)

  • Symbol: NCD5701ADR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncd5701adr2g-etched.step / ncd5701adr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncd5701adr2g.step / ncd5701adr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (20 pp, sha256 ea9003fdf65bc54d, retrieved 2026-10-25, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF