component
NCD57001DWR2G
Public Made by Adomby adom
onsemi Isolators - Gate Drivers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# NCD57001DWR2G++**onsemi** · Isolators - Gate Drivers · SOIC-16-300mil++NCD57001DWR2G from onsemi, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VEE2A | power_in | Output side negative power supply; requires good quality bypassing capacitor to GND2 placed close to pin for best results. |+| 2 | DESAT | bidirectional | Desaturation detection input with internal constant current source (0.45-0.6 mA) for programmable blanking delay; voltage range −9 to VDD2 + 0.3 V. |+| 3 | GND2 | power_in | Output side gate drive reference connecting to IGBT emitter or FET source. |+| 4 | N/C | unconnected | Not connected. |+| 5 | VDD2 | power_in | Output side positive power supply with operating range from UVLO2 (13.2 to 13.8 V typical) to 24 V maximum; requires bypassing capacitor to GND2. |+| 6 | OUT | output | Gate driver output providing up to 4 A source and 6 A sink current to IGBT/FET gate; actively pulled low during start-up and fault conditions. |+| 7 | CLAMP | bidirectional | Gate clamping input/output pin connected directly to IGBT/FET gate for parasitic turn-on protection; internal N-FET turns on when voltage falls below VEE2 + VCLAMP−THR (1.5 to 2.5 V). |+| 8 | VEE2 | power_in | Output side negative power supply with range −10 to 0 V; requires good quality bypassing capacitor to GND2 placed close to pin for best results. |+| 9 | GND1 | power_in | Input side ground reference. |+| 10 | IN+ | input | Non-inverted gate driver input internally clamped to VDD1 with 50 kΩ pull-down resistor; requires minimum 40 ns pulse width for guaranteed output response. |+| 11 | IN− | input | Inverted gate driver input internally clamped to VDD1 with 50 kΩ pull-up resistor; requires minimum 40 ns pulse width for guaranteed output response. |+| 12 | RDY | output | Power good indication output active high when VDD2 exceeds UVLO2 threshold (13.2-13.8 V); open-drain with 50 kΩ pull-up resistor and maximum 200 ns low duration on UVLO2 event. |+| 13 | /FLT | output | Active-low fault output indicating desaturation condition and driver shutdown; open-drain output that allows multiple drivers to be OR'ed together. |+| 14 | /RST | input | Active-low reset input with 50 kΩ pull-up resistor; requires minimum 800 ns pulse width to reset fault latch. |+| 15 | VDD1 | power_in | Input side power supply with operating range from UVLO1 (2.4 V disable, 3.0 V typical enable) to 5.5 V maximum; supports both 3.3 V and 5 V logic levels. |+| 16 | GND1A | power_in | Input side ground reference for improved current distribution. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | SOIC-16-300mil |+| Category | Power Management (PMIC) |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `NCD57001DWR2G`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)+- 3D model files: `ncd57001dwr2g-etched.step` / `ncd57001dwr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncd57001dwr2g.step` / `ncd57001dwr2g.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907876153114624) (13 pp, sha256 `f2926c50e61b5cb9`, retrieved 2026-09-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ncd57001dwr2g-datasheet.pdf)
page.jsonadded+191@@ -0,0 +1,191 @@+{+ "slug": "ncd57001dwr2g",+ "version": "0.1.0",+ "type": "component",+ "description": "onsemi Isolators - Gate Drivers, SOIC-16-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "ncd57001dwr2g",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ncd57001dwr2g.kicad_sym",+ "ncd57001dwr2g.kicad_mod",+ "ncd57001dwr2g.glb",+ "ncd57001dwr2g.step",+ "ncd57001dwr2g.lbr",+ "docs/hero.png",+ "docs/ncd57001dwr2g-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "NCD57001DWR2G",+ "manufacturer": "onsemi",+ "package": "SOIC-16-300mil",+ "pin_count": 16,+ "category": "Power Management (PMIC)",+ "subcategory": "Isolators - Gate Drivers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907876153114624",+ "parts": {+ "symbol": "ncd57001dwr2g.kicad_sym",+ "footprint": "ncd57001dwr2g.kicad_mod",+ "model_3d": "ncd57001dwr2g-etched.glb",+ "model_3d_plain": "ncd57001dwr2g.glb",+ "model_3d_step": "ncd57001dwr2g-etched.step",+ "model_3d_step_plain": "ncd57001dwr2g.step",+ "lbr": "ncd57001dwr2g.lbr"+ },+ "distributor_links": {+ "lcsc": "C512996"+ },+ "pins": [+ {+ "number": "1",+ "name": "VEE2A",+ "type": "power_in",+ "description": "Output side negative power supply; requires good quality bypassing capacitor to GND2 placed close to pin for best results."+ },+ {+ "number": "2",+ "name": "DESAT",+ "type": "bidirectional",+ "description": "Desaturation detection input with internal constant current source (0.45-0.6 mA) for programmable blanking delay; voltage range −9 to VDD2 + 0.3 V."+ },+ {+ "number": "3",+ "name": "GND2",+ "type": "power_in",+ "description": "Output side gate drive reference connecting to IGBT emitter or FET source."+ },+ {+ "number": "4",+ "name": "N/C",+ "type": "unconnected",+ "description": "Not connected."+ },+ {+ "number": "5",+ "name": "VDD2",+ "type": "power_in",+ "description": "Output side positive power supply with operating range from UVLO2 (13.2 to 13.8 V typical) to 24 V maximum; requires bypassing capacitor to GND2."+ },+ {+ "number": "6",+ "name": "OUT",+ "type": "output",+ "description": "Gate driver output providing up to 4 A source and 6 A sink current to IGBT/FET gate; actively pulled low during start-up and fault conditions."+ },+ {+ "number": "7",+ "name": "CLAMP",+ "type": "bidirectional",+ "description": "Gate clamping input/output pin connected directly to IGBT/FET gate for parasitic turn-on protection; internal N-FET turns on when voltage falls below VEE2 + VCLAMP−THR (1.5 to 2.5 V)."+ },+ {+ "number": "8",+ "name": "VEE2",+ "type": "power_in",+ "description": "Output side negative power supply with range −10 to 0 V; requires good quality bypassing capacitor to GND2 placed close to pin for best results."+ },+ {+ "number": "9",+ "name": "GND1",+ "type": "power_in",+ "description": "Input side ground reference."+ },+ {+ "number": "10",+ "name": "IN+",+ "type": "input",+ "description": "Non-inverted gate driver input internally clamped to VDD1 with 50 kΩ pull-down resistor; requires minimum 40 ns pulse width for guaranteed output response."+ },+ {+ "number": "11",+ "name": "IN−",+ "type": "input",+ "description": "Inverted gate driver input internally clamped to VDD1 with 50 kΩ pull-up resistor; requires minimum 40 ns pulse width for guaranteed output response."+ },+ {+ "number": "12",+ "name": "RDY",+ "type": "output",+ "description": "Power good indication output active high when VDD2 exceeds UVLO2 threshold (13.2-13.8 V); open-drain with 50 kΩ pull-up resistor and maximum 200 ns low duration on UVLO2 event."+ },+ {+ "number": "13",+ "name": "/FLT",+ "type": "output",+ "description": "Active-low fault output indicating desaturation condition and driver shutdown; open-drain output that allows multiple drivers to be OR'ed together."+ },+ {+ "number": "14",+ "name": "/RST",+ "type": "input",+ "description": "Active-low reset input with 50 kΩ pull-up resistor; requires minimum 800 ns pulse width to reset fault latch."+ },+ {+ "number": "15",+ "name": "VDD1",+ "type": "power_in",+ "description": "Input side power supply with operating range from UVLO1 (2.4 V disable, 3.0 V typical enable) to 5.5 V maximum; supports both 3.3 V and 5 V logic levels."+ },+ {+ "number": "16",+ "name": "GND1A",+ "type": "power_in",+ "description": "Input side ground reference for improved current distribution."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin 16 (GND1A) is listed in the PIN ASSIGNMENT diagram on page 1 and referenced in the Simplified Ap"+ ],+ "pages_sent": 13,+ "cost_usd": 0.4424,+ "at": "2026-09-21T22:11:08"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907876153114624",+ "pages": 13,+ "sha256": "f2926c50e61b5cb9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}