component
NCA9548-DTSXR
Public Made by Adomby adom
NOVOSENSE Power Distribution Switches, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCA9548-DTSXR
NOVOSENSE · Power Distribution Switches · TSSOP-24
NCA9548-DTSXR from NOVOSENSE, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Address input 0 that must be connected directly to VCC or ground to set the device slave address. |
| 2 | A1 | input | Address input 1 that must be connected directly to VCC or ground to set the device slave address. |
| 3 | RESET | input | Active-low reset input that resets the I2C state machine and deselects all channels when pulled low, and should be connected to VCC or the pull-up reference through a pull-up resistor if not used. |
| 4 | SD0 | bidirectional | Serial data line for downstream channel 0, which must be connected to the channel 0 pull-up reference through a pull-up resistor. |
| 5 | SC0 | bidirectional | Serial clock line for downstream channel 0, which must be connected to the channel 0 pull-up reference through a pull-up resistor. |
| 6 | SD1 | bidirectional | Serial data line for downstream channel 1, which must be connected to the channel 1 pull-up reference through a pull-up resistor. |
| 7 | SC1 | bidirectional | Serial clock line for downstream channel 1, which must be connected to the channel 1 pull-up reference through a pull-up resistor. |
| 8 | SD2 | bidirectional | Serial data line for downstream channel 2, which must be connected to the channel 2 pull-up reference through a pull-up resistor. |
| 9 | SC2 | bidirectional | Serial clock line for downstream channel 2, which must be connected to the channel 2 pull-up reference through a pull-up resistor. |
| 10 | SD3 | bidirectional | Serial data line for downstream channel 3, which must be connected to the channel 3 pull-up reference through a pull-up resistor. |
| 11 | SC3 | bidirectional | Serial clock line for downstream channel 3, which must be connected to the channel 3 pull-up reference through a pull-up resistor. |
| 12 | GND | power_in | Ground reference for the device. |
| 13 | SD4 | bidirectional | Serial data line for downstream channel 4, which must be connected to the channel 4 pull-up reference through a pull-up resistor. |
| 14 | SC4 | bidirectional | Serial clock line for downstream channel 4, which must be connected to the channel 4 pull-up reference through a pull-up resistor. |
| 15 | SD5 | bidirectional | Serial data line for downstream channel 5, which must be connected to the channel 5 pull-up reference through a pull-up resistor. |
| 16 | SC5 | bidirectional | Serial clock line for downstream channel 5, which must be connected to the channel 5 pull-up reference through a pull-up resistor. |
| 17 | SD6 | bidirectional | Serial data line for downstream channel 6, which must be connected to the channel 6 pull-up reference through a pull-up resistor. |
| 18 | SC6 | bidirectional | Serial clock line for downstream channel 6, which must be connected to the channel 6 pull-up reference through a pull-up resistor. |
| 19 | SD7 | bidirectional | Serial data line for downstream channel 7, which must be connected to the channel 7 pull-up reference through a pull-up resistor. |
| 20 | SC7 | bidirectional | Serial clock line for downstream channel 7, which must be connected to the channel 7 pull-up reference through a pull-up resistor. |
| 21 | A2 | input | Address input 2 that must be connected directly to VCC or ground to set the device slave address. |
| 22 | SCL | bidirectional | Upstream serial clock line from the I2C master, which must be connected to the master pull-up reference through a pull-up resistor. |
| 23 | SDA | bidirectional | Upstream serial data line from the I2C master, which must be connected to the master pull-up reference through a pull-up resistor. |
| 24 | VCC | power_in | Supply voltage, 1.65 V to 5.5 V, which also sets the maximum pass-gate high voltage on the channels. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NOVOSENSE |
| Package | TSSOP-24 |
| Category | Power Management (PMIC) |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 1.65 | 5.5 | V | 4 | ||
| Operating free-air temperature | TA | -40 | 105 | ℃ | 4 | ||
| Low-level input voltage (SCL, SDA) | VIL | -0.5 | V | 4 | |||
| High-level input voltage (SCL, SDA) | VIH | 6 | V | 4 | |||
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input/output voltage | VI/VO | -0.5 | 7 | V | 4 | ||
| Input current | II | -25 | 25 | mA | 4 | ||
| Output current | IO | -25 | 25 | mA | VO<0V | 4 | |
| Continuous current through VCC or GND | ICC | -100 | 100 | mA | 4 | ||
| Operating temperature | Topr | -40 | 105 | ℃ | 4 | ||
| Storage temperature | Tstg | -65 | 150 | ℃ | 4 | ||
| Electrostatic discharge, human-body model | HBM | -2000 | 2000 | V | 4 | ||
| Electrostatic discharge, charged-device model | CDM | -1000 | 1000 | V | 4 | ||
| Power on Reset falling | VPORF | 0.9 | 1.08 | V | no load; VI = VCC or GND | 5 | |
| Power on Reset rising | VPORR | 1.15 | 1.4 | V | no load; VI = VCC or GND | 5 | |
| Supply current | ICC | 10 | µA | Operating mode; VCC = 5.5 V; VI=VCC or GND; no load; fSCL = 100 kHz | 5 | ||
| Standby current | Istb | 0.7 | 5 | µA | Standby mode; VCC = 5.5 V; VI=VCC or GND; no load | 5 | |
| LOW-level input voltage (SCL, SDA) | VIL | -0.5 | V | 5 | |||
| HIGH-level input voltage (SCL, SDA) | VIH | 6 | V | When VCC=1.65V-2.3V, the minimum value of VIH is 0.8*VCC | 5 | ||
| LOW-level output current | IOL | 2.5 | 15 | mA | VOL = 0.4 V | 5 | |
| LOW-level output current | IOL | 5 | 20 | mA | VOL=0.6V | 5 | |
| Input leakage current (SCL, SDA) | IL | -1 | 1 | µA | VI = VCC or GND | 5 | |
| Input capacitance (SCL, SDA) | Ci | 15 | pF | VI = GND | 5 | ||
| LOW-level input voltage (select inputs A0, A1, A2, RESET) | VIL | -0.5 | V | 5 | |||
| HIGH-level input voltage (select inputs A0, A1, A2, RESET) | VIH | 6 | V | When VCC=1.65V-2.3V, the minimum value of VIH is 0.8*VCC | 5 | ||
| Input capacitance (select inputs) | Ci | 1.6 | 3 | pF | VI = GND | 6 | |
| On-state resistance | Ron | 4 | 14 | 20 | Ω | Vo=0.4 V, IO = 15 mA, VCC = 4.5V | 6 |
| On-state resistance | Ron | 5 | 16 | 25 | Ω | Vo=0.4 V, IO = 15 mA, VCC = 3V | 6 |
| On-state resistance | Ron | 6 | 19 | 30 | Ω | Vo=0.4 V, IO = 10 mA, VCC = 2.3V | 6 |
| On-state resistance | Ron | 10 | 28 | 40 | Ω | Vo=0.4 V, IO = 10 mA, VCC = 1.65V | 6 |
| Switch output voltage | VO(SW) | 2.6 | 4.5 | V | VCC = 4.5V to 5.5 V, IO(SW) = -100uA | 6 | |
| Switch output voltage | VO(SW) | 1.6 | 2.8 | V | VCC = 3 V to 3.6 V, IO(SW) = -100uA | 6 | |
| Switch output voltage | VO(SW) | 1 | 1.9 | V | VCC = 2.3 V to 2.7 V, IO(SW) = -100uA | 6 | |
| Switch output voltage | VO(SW) | 0.5 | 1.2 | V | VCC = 1.65 V to 1.95 V, IO(SW) = -100uA | 6 | |
| Leakage current (pass gate switch) | IL | -1 | 1 | µA | VI = VCC or GND | 6 | |
| Input/output capacitance | Cio | 6 | pF | VI=GND | 6 | ||
| SCL clock frequency (standard-mode) | fSCL | 0 | 100 | kHz | Standard-mode I2C-bus | 7 | |
| SCL clock frequency (fast-mode) | fSCL | 0 | 400 | kHz | Fast-mode I2C-bus | 7 | |
| bus free time between a STOP and START condition (fast-mode) | tBUF | 1.3 | µs | Fast-mode I2C-bus | 7 | ||
| LOW period of the SCL clock (standard-mode) | tLOW | 4.7 | µs | Standard-mode I2C-bus | 7 | ||
| LOW period of the SCL clock (fast-mode) | tLOW | 1.3 | µs | Fast-mode I2C-bus | 7 | ||
| HIGH period of the SCL clock (standard-mode) | tHIGH | 4 | µs | Standard-mode I2C-bus | 7 | ||
| HIGH period of the SCL clock (fast-mode) | tHIGH | 0.6 | µs | Fast-mode I2C-bus | 7 | ||
| data set-up time (standard-mode) | tSU;DAT | 250 | ns | Standard-mode I2C-bus | 7 | ||
| data set-up time (fast-mode) | tSU;DAT | 100 | ns | Fast-mode I2C-bus | 7 | ||
| rise time of both SDA and SCL (standard-mode) | tr | 1000 | ns | Standard-mode I2C-bus | 7 | ||
| rise time of both SDA and SCL (fast-mode) | tr | 300 | ns | Fast-mode I2C-bus | 7 | ||
| fall time of both SDA and SCL (standard-mode) | tf | 300 | ns | Standard-mode I2C-bus | 7 | ||
| fall time of both SDA and SCL (fast-mode) | tf | 300 | ns | Fast-mode I2C-bus | 7 | ||
| data valid acknowledge time (standard-mode) | tVD;ACK | 0.3 | 3.45 | µs | Standard-mode I2C-bus | 7 | |
| data valid acknowledge time (fast-mode) | tVD;ACK | 0.1 | 0.9 | µs | Fast-mode I2C-bus | 7 | |
| Reset time (ACK bit) | trst | 600 | ns | 7 | |||
| Switch output voltage | VO(SW) | 3.64 | V | VCC = 5 V, IO(SW) = -100uA | 6 | ||
| Switch output voltage | VO(SW) | 2.15 | V | VCC = 3.3 V, IO(SW) = -100uA | 6 | ||
| Switch output voltage | VO(SW) | 1.46 | V | VCC = 2.5 V, IO(SW) = -100uA | 6 | ||
| Switch output voltage | VO(SW) | 0.99 | V | VCC = 1.8 V, IO(SW) = -100uA | 6 | ||
| Junction-to-ambient thermal resistance | θJA | 115.3 | ℃/W | 5 | |||
| Junction-to-case (top) thermal resistance | θJC(top) | 48.7 | ℃/W | 5 | |||
| Junction-to-board thermal resistance | θJB | 66.4 | ℃/W | 5 |
CAD (KiCad official)
- Symbol:
NCA9548-DTSXR - Footprint:
Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm - 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files:
nca9548-dtsxr-etched.step/nca9548-dtsxr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nca9548-dtsxr.step/nca9548-dtsxr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NOVOSENSE datasheet (25 pp, sha256
e72afc6384a16cfc, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).