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NCA9546-DTSPR
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NOVOSENSE Power Distribution Switches, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NCA9546-DTSPR
NOVOSENSE · Power Distribution Switches · TSSOP-16
NCA9546-DTSPR from NOVOSENSE, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Address input 0, to be connected directly to VCC or ground to set the device address. |
| 2 | A1 | input | Address input 1, to be connected directly to VCC or ground to set the device address. |
| 3 | RESET | input | Active-low reset input that resets the I2C state machine and deselects all channels; connect to VCC or VDPUM through a pull-up resistor if not used. |
| 4 | SD0 | bidirectional | Serial data 0 for downstream channel 0; connect to VDPU0 through a pull-up resistor. |
| 5 | SC0 | bidirectional | Serial clock 0 for downstream channel 0; connect to VDPU0 through a pull-up resistor. |
| 6 | SD1 | bidirectional | Serial data 1 for downstream channel 1; connect to VDPU1 through a pull-up resistor. |
| 7 | SC1 | bidirectional | Serial clock 1 for downstream channel 1; connect to VDPU1 through a pull-up resistor. |
| 8 | GND | power_in | Ground. |
| 9 | SD2 | bidirectional | Serial data 2 for downstream channel 2; connect to VDPU2 through a pull-up resistor. |
| 10 | SC2 | bidirectional | Serial clock 2 for downstream channel 2; connect to VDPU2 through a pull-up resistor. |
| 11 | SD3 | bidirectional | Serial data 3 for downstream channel 3; connect to VDPU3 through a pull-up resistor. |
| 12 | SC3 | bidirectional | Serial clock 3 for downstream channel 3; connect to VDPU3 through a pull-up resistor. |
| 13 | A2 | input | Address input 2, to be connected directly to VCC or ground to set the device address. |
| 14 | SCL | bidirectional | Upstream serial clock line from the master; connect to VDPUM through a pull-up resistor. |
| 15 | SDA | bidirectional | Upstream serial data line from the master; connect to VDPUM through a pull-up resistor. |
| 16 | VCC | power_in | Supply power; the recommended operating supply voltage range is 1.7 V to 5.5 V and it also limits the maximum passed high voltage through the pass gates. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NOVOSENSE |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage Range | VCC | 1.7 | 5.5 | V | 5 | ||
| Power On Reset falling | VPORF | 0.9 | 1.08 | V | no load; VI = VCC or GND | 5 | |
| Power On Reset rising | VPORR | 1.15 | 1.4 | V | no load; VI = VCC or GND | 5 | |
| Supply current | ICC | 10 | µA | Operating mode; VCC = 5.5 V; VI=VCC or GND; no load; fSCL = 100 kHz | 5 | ||
| Standby current | Istb | 0.3 | 5 | µA | Standby mode; VCC = 5.5 V; VI=VCC or GND; no load | 5 | |
| LOW-level input voltage (SCL, SDA) | VIL | -0.5 | V | 5 | |||
| HIGH-level input voltage (SCL, SDA) | VIH | 6 | V | When VCC=1.7V-2.3V, the minimum value of VIH is 0.8*VCC | 5 | ||
| LOW-level output current | IOL | 2.5 | 15 | mA | VOL=0.4V | 5 | |
| LOW-level output current | IOL | 4 | 20 | mA | VOL=0.6V | 5 | |
| Input leakage current (SCL, SDA) | IL | -1 | 1 | µA | VI = VCC or GND | 5 | |
| Input capacitance (SCL, SDA) | Ci | 15 | pF | VI = GND | 5 | ||
| LOW-level input voltage (A0, A1, A2, RESET) | VIL | -0.5 | V | 5 | |||
| HIGH-level input voltage (A0, A1, A2, RESET) | VIH | 6 | V | When VCC=1.7V-2.3V, the minimum value of VIH is 0.8*VCC | 5 | ||
| Leakage current (A0, A1, A2, RESET) | IL | -1 | 1 | µA | VI = VCC or GND | 5 | |
| Input capacitance (A0, A1, A2, RESET) | Ci | 1.6 | 3 | pF | VI = GND | 5 | |
| Pass gate on-state resistance | Ron | 4 | 14 | 20 | Ω | Vo=0.4 V, IO = 15 mA, VCC = 4.5V | 5 |
| Pass gate on-state resistance | Ron | 5 | 16 | 25 | Ω | Vo=0.4 V, IO = 15 mA, VCC = 3V | 5 |
| Pass gate on-state resistance | Ron | 6 | 19 | 30 | Ω | Vo=0.4 V, IO = 10 mA, VCC = 2.3V | 5 |
| Pass gate on-state resistance | Ron | 10 | 28 | 40 | Ω | Vo=0.4 V, IO = 10 mA, VCC = 1.7V | 5 |
| Switch output voltage | VO(SW) | 2.6 | 4.5 | V | VCC = 4.5V to 5.5 V, IO(SW) = -100uA | 5 | |
| Switch output voltage | VO(SW) | 1.6 | 2.8 | V | VCC = 3 V to 3.6 V, IO(SW) = -100uA | 5 | |
| Switch output voltage | VO(SW) | 1 | 1.9 | V | VCC = 2.3 V to 2.7 V, IO(SW) = -100uA | 5 | |
| Switch output voltage | VO(SW) | 0.5 | 1.2 | V | VCC = 1.7 V to 1.95 V, IO(SW) = -100uA | 5 | |
| Leakage current (switch I/O) | IL | -1 | 1 | µA | VI = VCC or GND | 5 | |
| Input/output capacitance | Cio | 6 | pF | VI=GND | 5 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input/output voltage | VI/VO | -0.5 | 7 | V | 4 | ||
| Input current | II | -25 | 25 | mA | 4 | ||
| Output current | IO | -25 | 25 | mA | VO<0V | 4 | |
| Continuous current through VCC or GND | ICC | -100 | 100 | mA | 4 | ||
| Operating Temperature | Topr | -40 | 105 | ℃ | 4 | ||
| Storage Temperature | Tstg | -65 | 150 | ℃ | 4 | ||
| Electrostatic discharge HBM | HBM | -2000 | 2000 | V | 4 | ||
| Electrostatic discharge CDM | CDM | -1000 | 1000 | V | 4 | ||
| Supply voltage | VCC | 1.7 | 5.5 | V | 4 | ||
| High-level input voltage | VIH | 6 | V | SCL, SDA | 4 | ||
| Low-level input voltage | VIL | -0.5 | V | SCL, SDA | 4 | ||
| Operating free-air temperature | TA | -40 | 105 | ℃ | 4 | ||
| SCL clock frequency | fSCL | 0 | 100 | kHz | Standard-mode I2C-bus | 6 | |
| SCL clock frequency | fSCL | 0 | 400 | kHz | Fast-mode I2C-bus | 6 | |
| data valid acknowledge time | tVD;ACK | 0.3 | 3.45 | µs | Standard-mode I2C-bus | 6 | |
| data valid acknowledge time | tVD;ACK | 0.1 | 0.9 | µs | Fast-mode I2C-bus | 6 | |
| data valid time | tVD;DAT | 300 | ns | Standard-mode I2C-bus | 6 | ||
| data valid time | tVD;DAT | 50 | ns | Fast-mode I2C-bus | 6 | ||
| data set-up time | tSU;DAT | 250 | ns | Standard-mode I2C-bus | 6 | ||
| data set-up time | tSU;DAT | 100 | ns | Fast-mode I2C-bus | 6 | ||
| LOW period of the SCL clock | tLOW | 4.7 | µs | Standard-mode I2C-bus | 6 | ||
| LOW period of the SCL clock | tLOW | 1.3 | µs | Fast-mode I2C-bus | 6 | ||
| HIGH period of the SCL clock | tHIGH | 4 | µs | Standard-mode I2C-bus | 6 | ||
| HIGH period of the SCL clock | tHIGH | 0.6 | µs | Fast-mode I2C-bus | 6 | ||
| fall time of both SDA and SCL signals | tf | 300 | ns | Standard-mode I2C-bus | 6 | ||
| rise time of both SDA and SCL signals | tr | 1000 | ns | Standard-mode I2C-bus | 6 | ||
| rise time of both SDA and SCL signals | tr | 300 | ns | Fast-mode I2C-bus | 6 | ||
| pulse width of spikes that must be suppressed by the input filter | tSP | 50 | ns | Standard-mode I2C-bus | 6 | ||
| Junction-to-ambient thermal resistance | θJA | 115.3 | ℃/W | 4 | |||
| Junction-to-case(top) thermal resistance | θJC(top) | 48.7 | ℃/W | 4 | |||
| Junction-to-board thermal resistance | θJB | 66.4 | ℃/W | 4 |
CAD (KiCad official)
- Symbol:
NCA9546-DTSPR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
nca9546-dtspr-etched.step/nca9546-dtspr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nca9546-dtspr.step/nca9546-dtspr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NOVOSENSE datasheet (23 pp, sha256
7799a0fd48b8441c, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NCA9546-DTSPR
**NOVOSENSE** · Power Distribution Switches · TSSOP-16
NCA9546-DTSPR from NOVOSENSE, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Address input 0, to be connected directly to VCC or ground to set the device address. |
| 2 | A1 | input | Address input 1, to be connected directly to VCC or ground to set the device address. |
| 3 | RESET | input | Active-low reset input that resets the I2C state machine and deselects all channels; connect to VCC or VDPUM through a pull-up resistor if not used. |
| 4 | SD0 | bidirectional | Serial data 0 for downstream channel 0; connect to VDPU0 through a pull-up resistor. |
| 5 | SC0 | bidirectional | Serial clock 0 for downstream channel 0; connect to VDPU0 through a pull-up resistor. |
| 6 | SD1 | bidirectional | Serial data 1 for downstream channel 1; connect to VDPU1 through a pull-up resistor. |
| 7 | SC1 | bidirectional | Serial clock 1 for downstream channel 1; connect to VDPU1 through a pull-up resistor. |
| 8 | GND | power_in | Ground. |
| 9 | SD2 | bidirectional | Serial data 2 for downstream channel 2; connect to VDPU2 through a pull-up resistor. |
| 10 | SC2 | bidirectional | Serial clock 2 for downstream channel 2; connect to VDPU2 through a pull-up resistor. |
| 11 | SD3 | bidirectional | Serial data 3 for downstream channel 3; connect to VDPU3 through a pull-up resistor. |
| 12 | SC3 | bidirectional | Serial clock 3 for downstream channel 3; connect to VDPU3 through a pull-up resistor. |
| 13 | A2 | input | Address input 2, to be connected directly to VCC or ground to set the device address. |
| 14 | SCL | bidirectional | Upstream serial clock line from the master; connect to VDPUM through a pull-up resistor. |
| 15 | SDA | bidirectional | Upstream serial data line from the master; connect to VDPUM through a pull-up resistor. |
| 16 | VCC | power_in | Supply power; the recommended operating supply voltage range is 1.7 V to 5.5 V and it also limits the maximum passed high voltage through the pass gates. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NOVOSENSE |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage Range | VCC | 1.7 | | 5.5 | V | | 5 |
| Power On Reset falling | VPORF | 0.9 | 1.08 | | V | no load; VI = VCC or GND | 5 |
| Power On Reset rising | VPORR | | 1.15 | 1.4 | V | no load; VI = VCC or GND | 5 |
| Supply current | ICC | | | 10 | µA | Operating mode; VCC = 5.5 V; VI=VCC or GND; no load; fSCL = 100 kHz | 5 |
| Standby current | Istb | | 0.3 | 5 | µA | Standby mode; VCC = 5.5 V; VI=VCC or GND; no load | 5 |
| LOW-level input voltage (SCL, SDA) | VIL | -0.5 | | | V | | 5 |
| HIGH-level input voltage (SCL, SDA) | VIH | | | 6 | V | When VCC=1.7V-2.3V, the minimum value of VIH is 0.8*VCC | 5 |
| LOW-level output current | IOL | 2.5 | 15 | | mA | VOL=0.4V | 5 |
| LOW-level output current | IOL | 4 | 20 | | mA | VOL=0.6V | 5 |
| Input leakage current (SCL, SDA) | IL | -1 | | 1 | µA | VI = VCC or GND | 5 |
| Input capacitance (SCL, SDA) | Ci | | | 15 | pF | VI = GND | 5 |
| LOW-level input voltage (A0, A1, A2, RESET) | VIL | -0.5 | | | V | | 5 |
| HIGH-level input voltage (A0, A1, A2, RESET) | VIH | | | 6 | V | When VCC=1.7V-2.3V, the minimum value of VIH is 0.8*VCC | 5 |
| Leakage current (A0, A1, A2, RESET) | IL | -1 | | 1 | µA | VI = VCC or GND | 5 |
| Input capacitance (A0, A1, A2, RESET) | Ci | | 1.6 | 3 | pF | VI = GND | 5 |
| Pass gate on-state resistance | Ron | 4 | 14 | 20 | Ω | Vo=0.4 V, IO = 15 mA, VCC = 4.5V | 5 |
| Pass gate on-state resistance | Ron | 5 | 16 | 25 | Ω | Vo=0.4 V, IO = 15 mA, VCC = 3V | 5 |
| Pass gate on-state resistance | Ron | 6 | 19 | 30 | Ω | Vo=0.4 V, IO = 10 mA, VCC = 2.3V | 5 |
| Pass gate on-state resistance | Ron | 10 | 28 | 40 | Ω | Vo=0.4 V, IO = 10 mA, VCC = 1.7V | 5 |
| Switch output voltage | VO(SW) | 2.6 | | 4.5 | V | VCC = 4.5V to 5.5 V, IO(SW) = -100uA | 5 |
| Switch output voltage | VO(SW) | 1.6 | | 2.8 | V | VCC = 3 V to 3.6 V, IO(SW) = -100uA | 5 |
| Switch output voltage | VO(SW) | 1 | | 1.9 | V | VCC = 2.3 V to 2.7 V, IO(SW) = -100uA | 5 |
| Switch output voltage | VO(SW) | 0.5 | | 1.2 | V | VCC = 1.7 V to 1.95 V, IO(SW) = -100uA | 5 |
| Leakage current (switch I/O) | IL | -1 | | 1 | µA | VI = VCC or GND | 5 |
| Input/output capacitance | Cio | | | 6 | pF | VI=GND | 5 |
| Supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| Input/output voltage | VI/VO | -0.5 | | 7 | V | | 4 |
| Input current | II | -25 | | 25 | mA | | 4 |
| Output current | IO | -25 | | 25 | mA | VO<0V | 4 |
| Continuous current through VCC or GND | ICC | -100 | | 100 | mA | | 4 |
| Operating Temperature | Topr | -40 | | 105 | ℃ | | 4 |
| Storage Temperature | Tstg | -65 | | 150 | ℃ | | 4 |
| Electrostatic discharge HBM | HBM | -2000 | | 2000 | V | | 4 |
| Electrostatic discharge CDM | CDM | -1000 | | 1000 | V | | 4 |
| Supply voltage | VCC | 1.7 | | 5.5 | V | | 4 |
| High-level input voltage | VIH | | | 6 | V | SCL, SDA | 4 |
| Low-level input voltage | VIL | -0.5 | | | V | SCL, SDA | 4 |
| Operating free-air temperature | TA | -40 | | 105 | ℃ | | 4 |
| SCL clock frequency | fSCL | 0 | | 100 | kHz | Standard-mode I2C-bus | 6 |
| SCL clock frequency | fSCL | 0 | | 400 | kHz | Fast-mode I2C-bus | 6 |
| data valid acknowledge time | tVD;ACK | 0.3 | | 3.45 | µs | Standard-mode I2C-bus | 6 |
| data valid acknowledge time | tVD;ACK | 0.1 | | 0.9 | µs | Fast-mode I2C-bus | 6 |
| data valid time | tVD;DAT | 300 | | | ns | Standard-mode I2C-bus | 6 |
| data valid time | tVD;DAT | 50 | | | ns | Fast-mode I2C-bus | 6 |
| data set-up time | tSU;DAT | 250 | | | ns | Standard-mode I2C-bus | 6 |
| data set-up time | tSU;DAT | 100 | | | ns | Fast-mode I2C-bus | 6 |
| LOW period of the SCL clock | tLOW | 4.7 | | | µs | Standard-mode I2C-bus | 6 |
| LOW period of the SCL clock | tLOW | 1.3 | | | µs | Fast-mode I2C-bus | 6 |
| HIGH period of the SCL clock | tHIGH | 4 | | | µs | Standard-mode I2C-bus | 6 |
| HIGH period of the SCL clock | tHIGH | 0.6 | | | µs | Fast-mode I2C-bus | 6 |
| fall time of both SDA and SCL signals | tf | | | 300 | ns | Standard-mode I2C-bus | 6 |
| rise time of both SDA and SCL signals | tr | | | 1000 | ns | Standard-mode I2C-bus | 6 |
| rise time of both SDA and SCL signals | tr | | | 300 | ns | Fast-mode I2C-bus | 6 |
| pulse width of spikes that must be suppressed by the input filter | tSP | | | 50 | ns | Standard-mode I2C-bus | 6 |
| Junction-to-ambient thermal resistance | θJA | | 115.3 | | ℃/W | | 4 |
| Junction-to-case(top) thermal resistance | θJC(top) | | 48.7 | | ℃/W | | 4 |
| Junction-to-board thermal resistance | θJB | | 66.4 | | ℃/W | | 4 |
## CAD (KiCad official)
- Symbol: `NCA9546-DTSPR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `nca9546-dtspr-etched.step` / `nca9546-dtspr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nca9546-dtspr.step` / `nca9546-dtspr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [NOVOSENSE datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603145364643848192) (23 pp, sha256 `7799a0fd48b8441c`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/nca9546-dtspr-datasheet.pdf)