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NCA9306DPH

Public Made by Adom

by adom

Nexperia Translators, Level Shifters, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCA9306DPH

Nexperia · Translators, Level Shifters · TSSOP-8

NCA9306DPH from Nexperia, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground (0 V).
2 refA power_in Low-voltage side reference supply voltage for SCLA and SDAA.
3 SCLA bidirectional Open-drain SCL data input/output on the A side, connected to SCLB when EN is HIGH and high-impedance when EN is LOW; requires a pull-up resistor.
4 SDAA bidirectional Open-drain SDA data input/output on the A side, connected to SDAB when EN is HIGH and high-impedance when EN is LOW; requires a pull-up resistor.
5 SDAB bidirectional Open-drain SDA data input/output on the B side, connected to SDAA when EN is HIGH and high-impedance when EN is LOW; requires a pull-up resistor.
6 SCLB bidirectional Open-drain SCL data input/output on the B side, connected to SCLA when EN is HIGH and high-impedance when EN is LOW; requires a pull-up resistor.
7 refB power_in High-voltage side reference supply voltage for SCLB and SDAB.
8 EN input Enable input, active HIGH; HIGH turns the translator switch on, LOW puts the channels in a high-impedance state.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-8
Category Logic
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VI -0.5 7 V pins refA, refB, SCLn, SDAn and EN 4
Input/output current II/O 128 mA pins refA, refB, SCLn, SDAn; continuous channel current 4
Input clamping current IIK -50 mA VI < 0 V 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 250 mW Tamb = -40 °C to +125 °C; SOT505-2; derates linearly with 4.6 mW/K above 96 °C 4
Input voltage VI 0 5 V pins refA, refB, SCLn, SDAn and EN 4
Input/output current II/O 64 mA pins refA, refB, SCLn, SDAn; continuous channel current 4
Ambient temperature Tamb -40 125 °C 4
Input clamping voltage VIK -1.2 V VEN = 0 V; II = -18 mA 4
Leakage current II 1 5 μA pins SCLn, SDAn, refA, refB and EN; VI = GND to 5.0 V 4
Input capacitance CI 6 pF pins refA, refB and EN; VI = 0 V or 3 V 4
OFF-state input/output capacitance Cio(off) 3 6 pF pins SCLn, SDAn; VO = 0 V or 3 V; VEN = 0.0 V 4
ON-state input/output capacitance Cio(on) 6 12.5 pF pins SCLn, SDAn; VO = 0 V or 3 V; VEN = 3.0 V 4
ON resistance RON 3 7 Ω VI = 0 V; Vpu = 5.0 V; IO = 64 mA; VrefA = 3.3 V 5
ON resistance RON 4 10 Ω VI = 0 V; Vpu = 5.0 V; IO = 64 mA; VrefA = 1.8 V 5
ON resistance RON 4 9 Ω VI = 0 V; VrefB = VEN = 5.0 V; IO = 32mA; VrefA = 1.8 V 5
ON resistance RON 3 8 Ω VI = 0 V; VrefB = VEN = 5.0 V; IO = 32mA; VrefA = 2.5 V 5
ON resistance RON 4 13 Ω VI = 1.8 V; VrefB = VEN = 5.0 V; IO = 15 mA; VrefA = 3.3 V 5
ON resistance RON 7 24 Ω VI = 1.0 V; VrefB = VEN = 3.3 V; IO = 10 mA; VrefA = 1.8 V 5
ON resistance RON 5 18 Ω VI = 0 V; VrefB = VEN = 3.3 V; IO = 10 mA; VrefA = 1.0 V 5
ON resistance RON 6 19 Ω VI = 0 V; VrefB = VEN = 1.8 V; IO = 10 mA; VrefA = 1.0 V 5
LOW to HIGH propagation delay, translating down tPLH 0.13 0.35 ns VIH = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 15 pF 6
LOW to HIGH propagation delay, translating down tPLH 0.22 0.59 ns VIH = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 30 pF 6
LOW to HIGH propagation delay, translating down tPLH 0.34 0.94 ns VIH = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 50 pF 6
LOW to HIGH propagation delay, translating down tPLH 0.09 0.25 ns VIH = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 15 pF 6
LOW to HIGH propagation delay, translating down tPLH 0.16 0.43 ns VIH = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 30 pF 6
LOW to HIGH propagation delay, translating down tPLH 0.24 0.69 ns VIH = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 50 pF 6
HIGH to LOW propagation delay, translating down tPHL 0.21 0.99 ns VIH = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 15 pF 6
HIGH to LOW propagation delay, translating down tPHL 0.36 1.78 ns VIH = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 30 pF 6
HIGH to LOW propagation delay, translating down tPHL 0.51 2.42 ns VIH = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 50 pF 6
HIGH to LOW propagation delay, translating down tPHL 0.12 0.45 ns VIH = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 15 pF 6
HIGH to LOW propagation delay, translating down tPHL 0.19 0.77 ns VIH = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 30 pF 6
HIGH to LOW propagation delay, translating down tPHL 0.3 1.17 ns VIH = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 50 pF 6
LOW to HIGH propagation delay, translating up tPLH 0.06 0.11 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 15 pF 6
LOW to HIGH propagation delay, translating up tPLH 0.14 0.32 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 30 pF 6
LOW to HIGH propagation delay, translating up tPLH 0.26 0.58 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 50 pF 6
LOW to HIGH propagation delay, translating up tPLH 0.06 0.13 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 15 pF 6
LOW to HIGH propagation delay, translating up tPLH 0.13 0.28 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 30 pF 6
LOW to HIGH propagation delay, translating up tPLH 0.2 0.5 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 50 pF 6
HIGH to LOW propagation delay, translating up tPHL 0.34 1.54 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 15 pF 6
HIGH to LOW propagation delay, translating up tPHL 0.6 2.6 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 30 pF 6
HIGH to LOW propagation delay, translating up tPHL 0.9 3.82 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 1.5 V; CL = 50 pF 6
HIGH to LOW propagation delay, translating up tPHL 0.17 0.71 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 15 pF 6
HIGH to LOW propagation delay, translating up tPHL 0.29 1.09 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 30 pF 6
HIGH to LOW propagation delay, translating up tPHL 0.45 1.67 ns VIH = VrefA; VEXT = Vpu = VrefA + 1 V; VrefA = 2.3 V; CL = 50 pF 6

CAD (KiCad official)

  • Symbol: NCA9306DPH
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: nca9306dph-etched.step / nca9306dph-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nca9306dph.step / nca9306dph.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 6a54035a2ae7acd8, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF