component

NC7WZ14P6X

Public Made by Adom

by adom

onsemi Inverters, SC-70-6(SOT-363). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs nc7wz14p6x: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
nc7wz14p6x-etched.fit.json nc7wz14p6x: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
nc7wz14p6x-etched.glb nc7wz14p6x: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
nc7wz14p6x-etched.step nc7wz14p6x: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
nc7wz14p6x.glb Publish 0.1.0 · Ray
nc7wz14p6x.kicad_mod Publish 0.1.0 · Ray
nc7wz14p6x.kicad_sym Publish 0.1.0 · Ray
nc7wz14p6x.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
nc7wz14p6x.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json nc7wz14p6x: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md nc7wz14p6x: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

NC7WZ14P6X

onsemi · Inverters · SC-70-6(SOT-363)

NC7WZ14P6X from onsemi, in a SC-70-6(SOT-363). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Schmitt-trigger inverter #1 input. Logic-level input with hysteresis (~1 V typ at 5 V VCC); tolerates up to 7 V independent of VCC. Must not be left floating.
2 GND power_in Ground reference (0 V) for the device.
3 A2 input Schmitt-trigger inverter #2 input. Logic-level input with hysteresis (~1 V typ at 5 V VCC); tolerates up to 7 V independent of VCC. Must not be left floating.
4 Y2 output Inverter #2 output (Y2 = /A2). CMOS push-pull output; ±24 mA drive at 3 V VCC. High-impedance when VCC = 0 V.
5 VCC power_in Positive supply voltage. Operating range 1.65 V to 5.5 V; data-retention minimum 1.5 V. Bypass with a local decoupling capacitor near this pin.
6 Y1 output Inverter #1 output (Y1 = /A1). CMOS push-pull output; ±24 mA drive at 3 V VCC. High-impedance when VCC = 0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SC-70-6(SOT-363)
Category Logic
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • NC7WZ14P6X
  • NC7WZ14P6XEP6X
  • NC7WZ14P6XL6X
  • NC7WZ14P6XFHX

CAD (KiCad official)

  • Symbol: NC7WZ14P6X
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6(SOT-363) (KiCad packages3D, STEP)
  • 3D model files: nc7wz14p6x-etched.step / nc7wz14p6x-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nc7wz14p6x.step / nc7wz14p6x.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
nc7wz14p6x.step 99 KB You want the bare part, or you mark your own boards.
nc7wz14p6x-etched.step 1.6 MB You want the part with NC7WZ14P6X already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 410 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (9 pp, sha256 a7fb3886682c50bc, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF