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NBA3N206SDR2G

Public Made by Adom

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onsemi LVDS ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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NBA3N206SDR2G

onsemi · LVDS ICs · SOIC-8

NBA3N206SDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R output Receiver output pin.
2 RE input Receiver enable input pin: LOW activates the receiver (LOW = Active) and HIGH places the receiver output in High Z; the open default is HIGH.
3 DE input Driver enable input pin: HIGH activates the driver and LOW places the driver output in High Z; the open default is LOW.
4 D input Driver input pin.
5 GND power_in Ground supply pin that must be connected to the power supply to guarantee proper operation.
6 A bidirectional Transceiver true input/output pin for the M-LVDS bus.
7 B bidirectional Transceiver invert input/output pin for the M-LVDS bus.
8 VCC power_in Power supply pin that must be connected to the power supply to guarantee proper operation, with VCC = 3.3 ±10% V (3.0 to 3.6 V).

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC -0.5 4 V -0.5 ≤ VCC ≤ 4.0 3
Input Voltage VIN -0.5 4 V D, DE, RE 3
Input Voltage VIN -1.8 4 V A, B 3
Output Voltage IOUT -0.3 4 V R 3
Output Voltage IOUT -1.8 4 V A, B 3
Operating Temperature Range, Industrial TA -40 125 °C 3
Operating Supply Voltage Range VCC 3 3.6 V VCC = 3.3 ±10% 1
Storage Temperature Range Tstg -65 150 °C 3
Thermal Resistance (Junction-to-Case) θJC 41 44 °C/W SOIC-8, Note 2 3
Wave Solder Tsol 265 °C 3
Input HIGH Voltage VIH 2 V 4
Input LOW Voltage VIL 0.8 V 4
Voltage at any bus terminal VBUS -1.4 3.8 V VA, VB, VY or VZ 4
Differential output voltage magnitude /VAB/ 440 690 mV see Figure 4 4
Change in Differential output voltage magnitude between logic states /VAB/ -50 50 mV see Figure 4 4
Steady state common mode output voltage VOS(SS) 0.8 1.2 V see Figure 5 4
Change in Steady state common mode output voltage between logic states VOS(SS) -50 50 mV see Figure 5 4
Peak-to-peak common-mode output voltage VOS(PP) 150 mV see Figure 5 4
Maximum steady-state open-circuit output voltage VAOC 0 2.4 V see Figure 9 4
Voltage overshoot, low-to-high level output VP(H) 1.2 V VSS, see Figure 7 4
Voltage overshoot, high-to-low level output VP(L) -0.2 V VSS, see Figure 7 4
High-level input current (D, DE) IIH 0 10 uA VIH = 2 V 4
Low-level input current (D, DE) IIL 0 10 uA VIL = 0.8 V 4
Differential short-circuit output current magnitude JIOSJ 24 mA see Figure 6 4
High-impedance state output current (driver only) IOZ -15 10 uA -1.4 V ≤ (VA or VB) ≤ 3.8 V, other output at 1.2 V 4
Power-off output current (0 V ≤ VCC ≤ 1.5 V) IO(OFF) -10 10 uA -1.4 V ≤ (VA or VB) ≤ 3.8 V, other output at 1.2 V 4
Positive-going Differential Input voltage Threshold VIT+ 150 mV Type 2, see Figure 11 & Table 8 4
Negative-going Differential Input voltage Threshold VIT− 50 mV Type 2, see Figure 11 & Table 8 4
High-level output voltage VOH 2.4 V IOH = -8 mA 4
Low-level output voltage VOL 0.4 V IOL = 8 mA 4
RE High-level input current IIH -10 0 A VIH = 2 V 4
RE Low-level input current IIL -10 0 A VIL = 0.8 V 4
High-impedance state output current IOZ -10 15 A VO = 0 V of 3.6 V 4
Input Capacitance CA / CB 3 pF VI = 0.4 sin(30E6πt) + 0.5 V, other outputs at 1.2 V, HP4194A 4
Differential Input Capacitance CAB 2.5 pF VAB = 0.4 sin(30E6πt) V, other outputs at 1.2 V, HP4194A 4
Input Capacitance Balance CA/B 99 101 % (CA/CB) 4
Input Current IA -32 32 uA Receiver or Transceiver with Driver Disabled, VB = 1.2 V 5
Differential Input Current IAB -4 4 uA Receiver or Transceiver with driver disabled (IA−IB), VA = VB, −1.4 ≤ VA ≤ 3.8 V 5
Receiver Input or Transceiver Input/Output Power Off Differential Input Current IAB(OFF) -4 4 uA VA = VB, 0 ≤ VCC ≤ 1.5 V, −1.4 ≤ VA ≤ 3.8 V 5
Transceiver Input Capacitance with Driver Disabled CA 5 pF VA = 0.4 sin(30E6πt) + 0.5 V, VB = 1.2 V, HP4194A 5
Transceiver Differential Input Capacitance with Driver Disabled CAB 3 pF VA = 0.4 sin(30E6t) + 0.5 V, VB = 1.2 V, HP4194A 5
Propagation Delay tPLH / tPHL 1 1.5 2.4 ns see Figure 7 5
Disable Time HIGH or LOW state to High Impedance tPHZ / tPLZ 7 ns see Figure 8 5
Enable Time High Impedance to HIGH or LOW state tPZH / tPZL 7 ns see Figure 8 5
Pulse Skew (/tPLH − tPHL/) tSK(P) 0 150 ps see Figure 7 5
Device to Device Skew tSK(PP) 1 ns similar path and conditions, see Figure 7 5
Period Jitter RMS tJIT(PER) 2 3.5 ps 100 MHz, Source tr/tf 0.5 ns, 30k samples, see Figure 10 5
Peak-to-peak Jitter tJIT(PP) 30 150 ps 200 Mbps 2^15-1 PRBS, Source tr/tf 0.5 ns, 100k samples, see Figure 10 5
Differential output rise and fall times tr / tf 0.9 1.6 ns see Figure 7 5
Propagation Delay tPLH / tPHL 2 6 ns see Figure 12 6
Disable Time HIGH or LOW state to High Impedance tPHZ / tPLZ 10 ns see Figure 13 6
Enable Time High Impedance to HIGH or LOW state tPZH / tPZL 18 ns see Figure 13 6
Pulse Skew (/tPLH − tPHL/) tSK(P) 300 500 ps Type 2, CL = 5 pF, see Figure 14 6
Device to Device Skew tSK(PP) 1 ns CL = 5 pF, see Figure 12 6
Period Jitter RMS tJIT(PER) 4 8 ps 100 MHz, Source tr/tf 0.5 ns, 30k samples, see Figure 14 6
Peak-to-peak Jitter tJIT(PP) 450 900 ps Type 2, 200 Mbps 2^15-1 PRBS, see Figure 14 6
Differential output rise and fall times tr / tf 1 2.3 ns CL = 15 pF, see Figure 14 6
Thermal Resistance (Junction-to-Ambient) θJA 190 °C/W 0 lfpm, SOIC-8 3
Thermal Resistance (Junction-to-Ambient) θJA 130 °C/W 500 lfpm, SOIC-8 3

CAD (KiCad official)

  • Symbol: NBA3N206SDR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: nba3n206sdr2g-etched.step / nba3n206sdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nba3n206sdr2g.step / nba3n206sdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (18 pp, sha256 c6be85e6bfb737bf, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF