component
NAU7802SGI
Public Made by Adomby adom
Nuvoton Tech Analog To Digital Converters (ADC), SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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page.json+18−15@@ -38,43 +38,43 @@ "number": "1", "name": "REFP", "type": "input",- "description": "Positive reference input accepting VREFN+1.5V to AVDD+0.1V (absolute max \u22120.3V to AVDD+0.3V)."+ "description": "Positive reference input accepting VREFN+1.5V to AVDD+0.1V (absolute max −0.3V to AVDD+0.3V)." }, { "number": "2", "name": "VIN1N", "type": "input",- "description": "Inverting input for channel 1, common-mode AVSS+1.5V to AVDD\u22121.5V (PGA gains 64\u2212128) or AVSS\u22120.1V to AVDD+0.1V (PGA bypass mode)."+ "description": "Inverting input for channel 1, common-mode AVSS+1.5V to AVDD−1.5V (PGA gains 64−128) or AVSS−0.1V to AVDD+0.1V (PGA bypass mode)." }, { "number": "3", "name": "VIN1P", "type": "input",- "description": "Non-inverting input for channel 1, common-mode AVSS+1.5V to AVDD\u22121.5V (PGA gains 64\u2212128) or AVSS\u22120.1V to AVDD+0.1V (PGA bypass mode)."+ "description": "Non-inverting input for channel 1, common-mode AVSS+1.5V to AVDD−1.5V (PGA gains 64−128) or AVSS−0.1V to AVDD+0.1V (PGA bypass mode)." }, { "number": "4", "name": "VIN2N", "type": "input",- "description": "Inverting input for channel 2, common-mode AVSS+1.5V to AVDD\u22121.5V (PGA gains 64\u2212128) or AVSS\u22120.1V to AVDD+0.1V (PGA bypass mode)."+ "description": "Inverting input for channel 2, common-mode AVSS+1.5V to AVDD−1.5V (PGA gains 64−128) or AVSS−0.1V to AVDD+0.1V (PGA bypass mode)." }, { "number": "5", "name": "VIN2P", "type": "input",- "description": "Non-inverting input for channel 2, common-mode AVSS+1.5V to AVDD\u22121.5V (PGA gains 64\u2212128) or AVSS\u22120.1V to AVDD+0.1V (PGA bypass mode)."+ "description": "Non-inverting input for channel 2, common-mode AVSS+1.5V to AVDD−1.5V (PGA gains 64−128) or AVSS−0.1V to AVDD+0.1V (PGA bypass mode)." }, { "number": "6", "name": "VBG", "type": "output",- "description": "Bandgap reference voltage output, 109mV at 25\u00b0C with 360\u00b5V/\u00b0C temperature coefficient; bypass with 0.1\u00b5F capacitor to AVSS."+ "description": "Bandgap reference voltage output, 109mV at 25°C with 360µV/°C temperature coefficient; bypass with 0.1µF capacitor to AVSS." }, { "number": "7", "name": "REFN", "type": "input",- "description": "Negative reference input accepting \u22120.1V to REFP\u22121.5V (absolute max \u22120.3V to AVDD+0.3V)."+ "description": "Negative reference input accepting −0.1V to REFP−1.5V (absolute max −0.3V to AVDD+0.3V)." }, { "number": "8",@@ -92,43 +92,43 @@ "number": "10", "name": "XIN", "type": "input",- "description": "External crystal oscillator input, 4.9152MHz \u00b13% or external clock input (absolute max \u22120.3V to DVDD+0.3V)."+ "description": "External crystal oscillator input, 4.9152MHz ±3% or external clock input (absolute max −0.3V to DVDD+0.3V)." }, { "number": "11", "name": "XOUT", "type": "output",- "description": "External crystal oscillator output (absolute max \u22120.3V to DVDD+0.3V)."+ "description": "External crystal oscillator output (absolute max −0.3V to DVDD+0.3V)." }, { "number": "12", "name": "DRDY", "type": "output",- "description": "Data Ready output (CMOS driver), VOH=0.9\u00d7DVDD and VOL=0.2\u00d7DVDD, pulled high when new conversion data available; polarity configurable via REG0x01[7]."+ "description": "Data Ready output (CMOS driver), VOH=0.9×DVDD and VOL=0.2×DVDD, pulled high when new conversion data available; polarity configurable via REG0x01[7]." }, { "number": "13", "name": "SCLK", "type": "input",- "description": "Serial clock input for I2C interface, 0\u2212100kHz standard mode or 0\u2212400kHz fast mode (VIH\u22650.7\u00d7VDD, VIL\u22640.3\u00d7VDD)."+ "description": "Serial clock input for I2C interface, 0−100kHz standard mode or 0−400kHz fast mode (VIH≥0.7×VDD, VIL≤0.3×VDD)." }, { "number": "14", "name": "SDIO", "type": "bidirectional",- "description": "Serial data input/output for I2C interface, 0\u2212100kHz standard or 0\u2212400kHz fast mode, open-drain output from NAU7802 (VIH\u22650.7\u00d7VDD, VIL\u22640.3\u00d7VDD)."+ "description": "Serial data input/output for I2C interface, 0−100kHz standard or 0−400kHz fast mode, open-drain output from NAU7802 (VIH≥0.7×VDD, VIL≤0.3×VDD)." }, { "number": "15", "name": "DVDD", "type": "power_in",- "description": "Digital power supply, 2.7V to 5.5V; must be 0.3V above AVDD when using internal LDO (absolute max \u22120.3V to +6.0V)."+ "description": "Digital power supply, 2.7V to 5.5V; must be 0.3V above AVDD when using internal LDO (absolute max −0.3V to +6.0V)." }, { "number": "16", "name": "AVDD/LDO", "type": "power_in",- "description": "Analog power supply from internal LDO (2.4\u22124.5V selectable, requires \u22641\u03a9 ESR capacitor) or external 2.7\u22125.5V when LDO disabled (absolute max \u22120.3V to +6.0V)."+ "description": "Analog power supply from internal LDO (2.4−4.5V selectable, requires ≤1Ω ESR capacitor) or external 2.7−5.5V when LDO disabled (absolute max −0.3V to +6.0V)." } ], "provenance": {@@ -206,5 +206,8 @@ "docs/nau7802sgi-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }