component
N9105ESOP-AA
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PowTech(CR-PowTech(Shanghai)) Battery Management ICs, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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N9105ESOP-AA
PowTech(CR-PowTech(Shanghai)) · Battery Management ICs · SOP-16
N9105ESOP-AA from PowTech(CR-PowTech(Shanghai)), in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NCDRV | output | Charge N-MOSFET gate drive output, Hi-Z on a charge protection event, with 4-8 µA output current capability and a voltage range of VCC-35 V to VCC+0.3 V. |
| 2 | VM | input | Load-open detection and charger detection pin, with 50 µA sink capability for load-open detection and a voltage range of VSS-0.3 V to VCC+0.3 V. |
| 3 | NDDRV | output | Discharge N-MOSFET gate drive output, equal to VVREGH (8.0 to 13 V) when no discharge protection event and 0.4 V max when a discharge protection event occurs. |
| 4 | CS | input | Current sense voltage input for the three-stage discharge overcurrent detection, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 5 | CUVT | passive | External capacitor pin that sets the cell undervoltage protection delay (TCUV = 10 s/µF), sleep delay and overcurrent 1/2 delays, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 6 | COVT | passive | External capacitor pin that sets the cell overvoltage protection delay (TCOV = 10 s/µF) and temperature detection period, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 7 | VSS | power_in | Negative supply input of the chip (ground reference). |
| 8 | TS | input | Temperature sensing voltage input for the NTC thermistor, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 9 | VTD | passive | Discharge over-temperature threshold setting pin, set by external resistor R1 = 9*RDOT, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 10 | VTC | passive | Charge over-temperature and charge low-temperature threshold setting pin, set by external resistor R2 = 4.75*RCOT, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 11 | VC1 | input | Cell 1 positive and cell 2 negative input, with a cell voltage range of -0.3 to +8 V. |
| 12 | VC2 | input | Cell 2 positive and cell 3 negative input, with a cell voltage range of -0.3 to +8 V. |
| 13 | VC3 | input | Cell 3 positive and cell 4 negative input, with a cell voltage range of -0.3 to +8 V. |
| 14 | VC4 | input | Cell 4 positive and cell 5 negative input, with a cell voltage range of -0.3 to +8 V. |
| 15 | VC5 | input | Cell 5 positive input, with a cell voltage range of -0.3 to +8 V. |
| 16 | VCC | power_in | Positive supply input of the chip connected to the battery pack positive terminal, with an operating range of 4.0 to 25 V and an absolute maximum of VSS+35 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PowTech(CR-PowTech(Shanghai)) |
| Package | SOP-16 |
| Category | Power Management ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC input voltage operating range | VCC | 4 | 25 | V | 6 | ||
| Input current normal state | IVCC_NOR | 25 | 35 | µA | VCELL=3.6V | 6 | |
| Input current power-down state | IVCC_PD | 0.6 | 1 | µA | VCELL=1.8V | 6 | |
| Startup voltage | VPOR | 4.8 | V | 6 | |||
| Discharge MOSFET drive supply | VVREGH | 8 | 10.5 | 13 | V | VCC>VVREGH+1V | 6 |
| VC5 input current normal state | IVC5 | 12 | 15 | µA | VCELL=3.6V | 6 | |
| VC(n) input current normal state | IVCn | -0.5 | 0.5 | µA | VCELL=3.6V, n=1 ~ 4 | 6 | |
| Overcharge protection voltage | VCOV | -0.025 | 4.25 | 0.025 | V | N9105ESOP-AA; tolerance ±0.025V | 8 |
| Overcharge recovery voltage | VCOVR | -0.025 | 4.05 | 0.025 | V | N9105ESOP-AA; tolerance ±0.025V | 8 |
| Over-discharge protection voltage | VCUV | -0.08 | 2.7 | 0.08 | V | N9105ESOP-AA; tolerance ±0.08V | 8 |
| Over-discharge recovery voltage | VCUVR | -0.08 | 3 | 0.08 | V | N9105ESOP-AA; tolerance ±0.08V | 8 |
| Overcurrent 1 protection voltage | VPDOC1 | -0.01 | 0.1 | 0.01 | V | N9105ESOP-AA; tolerance ±0.01V | 8 |
| Overcurrent 2 protection voltage | VPDOC2 | -0.02 | 0.2 | 0.02 | V | N9105ESOP-AA; tolerance ±0.02V | 8 |
| Load short-circuit protection voltage | VPSC | -0.05 | 0.4 | 0.05 | V | N9105ESOP-AA; tolerance ±0.05V | 8 |
| Discharge overtemperature threshold accuracy | tDOT | -5 | 5 | °C | set by resistor at VTD pin | 6 | |
| Discharge overtemperature recovery threshold accuracy | tDOTR | -5 | 5 | °C | tDOTR = tDOT, tΔDOT | 6 | |
| Charge overtemperature threshold accuracy | tCOT | -5 | 5 | °C | set by resistor at VTC pin | 6 | |
| Charge overtemperature recovery threshold accuracy | tCOTR | -5 | 5 | °C | tCOTR = tCOT, tΔCOT | 6 | |
| Charge low-temperature threshold accuracy | tCUT | -5 | 5 | °C | set by resistor at VTC pin | 6 | |
| Charge low-temperature recovery threshold accuracy | tCUTR | -5 | 5 | °C | tCUTR = tCUT + tΔCUT | 6 | |
| Charge/discharge state detection voltage | VDSG | 2 | 3.5 | 6.5 | mV | 6 | |
| Overcharge protection delay time | TCOV | 0.6 | 1 | 1.4 | S | CCOVT=0.1μF | 6 |
| Over-discharge protection delay time | TCUV | 0.6 | 1 | 1.4 | S | CCUVT=0.1μF | 6 |
| Overcurrent 1 protection delay time | TPDOC1 | 0.6 | 1 | 1.4 | S | CCUVT=0.1μF | 6 |
| Overcurrent 2 protection delay time | TPDOC2 | 0.06 | 0.1 | 0.14 | S | CCUVT=0.1μF | 6 |
| Load short-circuit protection delay time | TPSC | 100 | 250 | 500 | μS | internal fixed delay | 6 |
| Temperature detection period | TTDET | 0.5 | 1 | 1.5 | S | CCOVT=0.1μF | 7 |
| NCDRV output current capability | INCDRV | 4 | 6 | 8 | μA | VCELL=3.6V, VNCDRV=VCC-3V | 7 |
| NDDRV output low voltage | VNDDRVL | 0.4 | V | discharge protection event | 7 | ||
| VM pin sink current capability | IVM | 50 | µA | load open detection | 7 | ||
| Over-discharge to sleep delay time | TCUV_PD | 11 | S | CCUVT=0.1μF | 6 | ||
| Discharge overtemperature recovery hysteresis | tΔDOT | 10 | °C | 6 | |||
| Charge overtemperature recovery hysteresis | tΔCOT | 5 | °C | 6 | |||
| Charge low-temperature recovery hysteresis | tΔCUT | 5 | °C | 6 | |||
| VCC pin input voltage | VCC | -0.3 | 35 | V | relative to VSS (VSS-0.3 to VSS+35) | 5 | |
| Low-voltage pins voltage | VIN_LV | -0.3 | 5.5 | V | CS, CUVT, COVT, TS, VTD, VTC; VSS-0.3 to VSS+5.5 | 5 | |
| VM pin voltage | VVM | -0.3 | 0.3 | V | VSS-0.3 to VCC+0.3 (max is VCC+0.3) | 5 | |
| Cell input pin voltage | VCELL | -0.3 | 8 | V | VC(n) to VC(n-1), n=2 to 5; VC1 to VSS | 5 | |
| NCDRV pin voltage | VNCDRV | -35 | 0.3 | V | VCC-35 to VCC+0.3 (relative to VCC) | 5 | |
| NDDRV pin voltage | VNDDRV | -0.3 | 15 | V | VSS-0.3 to VSS+15 | 5 | |
| ESD (HBM) | -2 | 2 | KV | ANSI/ESDA/JEDEC JS-001-2014 | 5 | ||
| Operating temperature range | TA | -40 | 85 | °C | 5 | ||
| Storage temperature range | TSTG | -40 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance (SOP-16) | θJA | 130 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
N9105ESOP-AA - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
n9105esop-aa-etched.step/n9105esop-aa-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);n9105esop-aa.step/n9105esop-aa.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PowTech(CR-PowTech(Shanghai)) datasheet (10 pp, sha256
37060a9434517c7e, retrieved 2026-10-30, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# N9105ESOP-AA
**PowTech(CR-PowTech(Shanghai))** · Battery Management ICs · SOP-16
N9105ESOP-AA from PowTech(CR-PowTech(Shanghai)), in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NCDRV | output | Charge N-MOSFET gate drive output, Hi-Z on a charge protection event, with 4-8 µA output current capability and a voltage range of VCC-35 V to VCC+0.3 V. |
| 2 | VM | input | Load-open detection and charger detection pin, with 50 µA sink capability for load-open detection and a voltage range of VSS-0.3 V to VCC+0.3 V. |
| 3 | NDDRV | output | Discharge N-MOSFET gate drive output, equal to VVREGH (8.0 to 13 V) when no discharge protection event and 0.4 V max when a discharge protection event occurs. |
| 4 | CS | input | Current sense voltage input for the three-stage discharge overcurrent detection, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 5 | CUVT | passive | External capacitor pin that sets the cell undervoltage protection delay (TCUV = 10 s/µF), sleep delay and overcurrent 1/2 delays, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 6 | COVT | passive | External capacitor pin that sets the cell overvoltage protection delay (TCOV = 10 s/µF) and temperature detection period, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 7 | VSS | power_in | Negative supply input of the chip (ground reference). |
| 8 | TS | input | Temperature sensing voltage input for the NTC thermistor, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 9 | VTD | passive | Discharge over-temperature threshold setting pin, set by external resistor R1 = 9*RDOT, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 10 | VTC | passive | Charge over-temperature and charge low-temperature threshold setting pin, set by external resistor R2 = 4.75*RCOT, with a voltage range of VSS-0.3 V to VSS+5.5 V. |
| 11 | VC1 | input | Cell 1 positive and cell 2 negative input, with a cell voltage range of -0.3 to +8 V. |
| 12 | VC2 | input | Cell 2 positive and cell 3 negative input, with a cell voltage range of -0.3 to +8 V. |
| 13 | VC3 | input | Cell 3 positive and cell 4 negative input, with a cell voltage range of -0.3 to +8 V. |
| 14 | VC4 | input | Cell 4 positive and cell 5 negative input, with a cell voltage range of -0.3 to +8 V. |
| 15 | VC5 | input | Cell 5 positive input, with a cell voltage range of -0.3 to +8 V. |
| 16 | VCC | power_in | Positive supply input of the chip connected to the battery pack positive terminal, with an operating range of 4.0 to 25 V and an absolute maximum of VSS+35 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PowTech(CR-PowTech(Shanghai)) |
| Package | SOP-16 |
| Category | Power Management ICs |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC input voltage operating range | VCC | 4 | | 25 | V | | 6 |
| Input current normal state | IVCC_NOR | | 25 | 35 | µA | VCELL=3.6V | 6 |
| Input current power-down state | IVCC_PD | | 0.6 | 1 | µA | VCELL=1.8V | 6 |
| Startup voltage | VPOR | | | 4.8 | V | | 6 |
| Discharge MOSFET drive supply | VVREGH | 8 | 10.5 | 13 | V | VCC>VVREGH+1V | 6 |
| VC5 input current normal state | IVC5 | 12 | | 15 | µA | VCELL=3.6V | 6 |
| VC(n) input current normal state | IVCn | -0.5 | | 0.5 | µA | VCELL=3.6V, n=1 ~ 4 | 6 |
| Overcharge protection voltage | VCOV | -0.025 | 4.25 | 0.025 | V | N9105ESOP-AA; tolerance ±0.025V | 8 |
| Overcharge recovery voltage | VCOVR | -0.025 | 4.05 | 0.025 | V | N9105ESOP-AA; tolerance ±0.025V | 8 |
| Over-discharge protection voltage | VCUV | -0.08 | 2.7 | 0.08 | V | N9105ESOP-AA; tolerance ±0.08V | 8 |
| Over-discharge recovery voltage | VCUVR | -0.08 | 3 | 0.08 | V | N9105ESOP-AA; tolerance ±0.08V | 8 |
| Overcurrent 1 protection voltage | VPDOC1 | -0.01 | 0.1 | 0.01 | V | N9105ESOP-AA; tolerance ±0.01V | 8 |
| Overcurrent 2 protection voltage | VPDOC2 | -0.02 | 0.2 | 0.02 | V | N9105ESOP-AA; tolerance ±0.02V | 8 |
| Load short-circuit protection voltage | VPSC | -0.05 | 0.4 | 0.05 | V | N9105ESOP-AA; tolerance ±0.05V | 8 |
| Discharge overtemperature threshold accuracy | tDOT | -5 | | 5 | °C | set by resistor at VTD pin | 6 |
| Discharge overtemperature recovery threshold accuracy | tDOTR | -5 | | 5 | °C | tDOTR = tDOT, tΔDOT | 6 |
| Charge overtemperature threshold accuracy | tCOT | -5 | | 5 | °C | set by resistor at VTC pin | 6 |
| Charge overtemperature recovery threshold accuracy | tCOTR | -5 | | 5 | °C | tCOTR = tCOT, tΔCOT | 6 |
| Charge low-temperature threshold accuracy | tCUT | -5 | | 5 | °C | set by resistor at VTC pin | 6 |
| Charge low-temperature recovery threshold accuracy | tCUTR | -5 | | 5 | °C | tCUTR = tCUT + tΔCUT | 6 |
| Charge/discharge state detection voltage | VDSG | 2 | 3.5 | 6.5 | mV | | 6 |
| Overcharge protection delay time | TCOV | 0.6 | 1 | 1.4 | S | CCOVT=0.1μF | 6 |
| Over-discharge protection delay time | TCUV | 0.6 | 1 | 1.4 | S | CCUVT=0.1μF | 6 |
| Overcurrent 1 protection delay time | TPDOC1 | 0.6 | 1 | 1.4 | S | CCUVT=0.1μF | 6 |
| Overcurrent 2 protection delay time | TPDOC2 | 0.06 | 0.1 | 0.14 | S | CCUVT=0.1μF | 6 |
| Load short-circuit protection delay time | TPSC | 100 | 250 | 500 | μS | internal fixed delay | 6 |
| Temperature detection period | TTDET | 0.5 | 1 | 1.5 | S | CCOVT=0.1μF | 7 |
| NCDRV output current capability | INCDRV | 4 | 6 | 8 | μA | VCELL=3.6V, VNCDRV=VCC-3V | 7 |
| NDDRV output low voltage | VNDDRVL | | | 0.4 | V | discharge protection event | 7 |
| VM pin sink current capability | IVM | | | 50 | µA | load open detection | 7 |
| Over-discharge to sleep delay time | TCUV_PD | | 11 | | S | CCUVT=0.1μF | 6 |
| Discharge overtemperature recovery hysteresis | tΔDOT | | 10 | | °C | | 6 |
| Charge overtemperature recovery hysteresis | tΔCOT | | 5 | | °C | | 6 |
| Charge low-temperature recovery hysteresis | tΔCUT | | 5 | | °C | | 6 |
| VCC pin input voltage | VCC | -0.3 | | 35 | V | relative to VSS (VSS-0.3 to VSS+35) | 5 |
| Low-voltage pins voltage | VIN_LV | -0.3 | | 5.5 | V | CS, CUVT, COVT, TS, VTD, VTC; VSS-0.3 to VSS+5.5 | 5 |
| VM pin voltage | VVM | -0.3 | | 0.3 | V | VSS-0.3 to VCC+0.3 (max is VCC+0.3) | 5 |
| Cell input pin voltage | VCELL | -0.3 | | 8 | V | VC(n) to VC(n-1), n=2 to 5; VC1 to VSS | 5 |
| NCDRV pin voltage | VNCDRV | -35 | | 0.3 | V | VCC-35 to VCC+0.3 (relative to VCC) | 5 |
| NDDRV pin voltage | VNDDRV | -0.3 | | 15 | V | VSS-0.3 to VSS+15 | 5 |
| ESD (HBM) | | -2 | | 2 | KV | ANSI/ESDA/JEDEC JS-001-2014 | 5 |
| Operating temperature range | TA | -40 | | 85 | °C | | 5 |
| Storage temperature range | TSTG | -40 | | 125 | °C | | 5 |
| Junction-to-ambient thermal resistance (SOP-16) | θJA | | 130 | | °C/W | | 5 |
## CAD (KiCad official)
- Symbol: `N9105ESOP-AA`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `n9105esop-aa-etched.step` / `n9105esop-aa-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `n9105esop-aa.step` / `n9105esop-aa.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [PowTech(CR-PowTech(Shanghai)) datasheet](docs/n9105esop-aa-datasheet.pdf) (10 pp, sha256 `37060a9434517c7e`, retrieved 2026-10-30, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/n9105esop-aa-datasheet.pdf)